4065

subx: 'compare'

Hopefully I've implemented the 'sense' of comparisons right..

6 files changed, 456 insertions, 0 deletions

diff --git a/html/subx/011direct_addressing.cc.html b/html/subx/011direct_addressing.cc.html
index a74072e6..8638ecfe 100644
--- a/html/subx/011direct_addressing.cc.html
+++ b/html/subx/011direct_addressing.cc.html
@@ -213,6 +213,51 @@ if ('onhashchange' in window) {
 <span id="L148" class="LineNr">148 </span>  <a href='010core.cc.html#L31'>OF</a> = <span class="Constant">false</span><span class="Delimiter">;</span>
 <span id="L149" class="LineNr">149 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
 <span id="L150" class="LineNr">150 </span><span class="Delimiter">}</span>
+<span id="L151" class="LineNr">151 </span>
+<span id="L152" class="LineNr">152 </span><span class="SalientComment">//:: compare</span>
+<span id="L153" class="LineNr">153 </span>
+<span id="L154" class="LineNr">154 </span><span class="Delimiter">:(scenario compare_r32_with_r32_greater)</span>
+<span id="L155" class="LineNr">155 </span><span class="Special">% Reg[0].i = 0x0a0b0c0d;</span>
+<span id="L156" class="LineNr">156 </span><span class="Special">% Reg[3].i = 0x0a0b0c07;</span>
+<span id="L157" class="LineNr">157 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L158" class="LineNr">158 </span>  <span class="Constant">39</span>  d8                                      <span class="Comment"># compare EBX (reg 3) with EAX (reg 0)</span>
+<span id="L159" class="LineNr">159 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L160" class="LineNr">160 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span>
+<span id="L161" class="LineNr">161 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L162" class="LineNr">162 </span>
+<span id="L163" class="LineNr">163 </span><span class="Delimiter">:(before &quot;End Single-Byte Opcodes&quot;)</span>
+<span id="L164" class="LineNr">164 </span><span class="Normal">case</span> <span class="Constant">0x39</span>: <span class="Delimiter">{</span>  <span class="Comment">// compare r32 with r/m32</span>
+<span id="L165" class="LineNr">165 </span>  <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L210'>next</a><span class="Delimiter">();</span>
+<span id="L166" class="LineNr">166 </span>  <span class="Normal">uint8_t</span> reg2 = <span class="Delimiter">(</span>modrm&gt;&gt;<span class="Constant">3</span><span class="Delimiter">)</span>&amp;<span class="Constant">0x7</span><span class="Delimiter">;</span>
+<span id="L167" class="LineNr">167 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;compare <a href='010core.cc.html#L15'>reg</a> &quot;</span> &lt;&lt; <a href='010core.cc.html#L228'>NUM</a><span class="Delimiter">(</span>reg2<span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot; with effective address&quot;</span> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L168" class="LineNr">168 </span>  <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span>
+<span id="L169" class="LineNr">169 </span>  <span class="Normal">int32_t</span> arg2 = Reg[reg2]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">;</span>
+<span id="L170" class="LineNr">170 </span>  <span class="Normal">int32_t</span> tmp1 = *arg1 - arg2<span class="Delimiter">;</span>
+<span id="L171" class="LineNr">171 </span>  SF = <span class="Delimiter">(</span>tmp1 &lt; <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L172" class="LineNr">172 </span>  <a href='010core.cc.html#L30'>ZF</a> = <span class="Delimiter">(</span>tmp1 == <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L173" class="LineNr">173 </span>  <span class="Normal">int64_t</span> tmp2 = *arg1 - arg2<span class="Delimiter">;</span>
+<span id="L174" class="LineNr">174 </span>  <a href='010core.cc.html#L31'>OF</a> = <span class="Delimiter">(</span>tmp1 != tmp2<span class="Delimiter">);</span>
+<span id="L175" class="LineNr">175 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;SF=&quot;</span> &lt;&lt; SF &lt;&lt; <span class="Constant">&quot;; ZF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L30'>ZF</a> &lt;&lt; <span class="Constant">&quot;; OF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L31'>OF</a> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L176" class="LineNr">176 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
+<span id="L177" class="LineNr">177 </span><span class="Delimiter">}</span>
+<span id="L178" class="LineNr">178 </span>
+<span id="L179" class="LineNr">179 </span><span class="Delimiter">:(scenario compare_r32_with_r32_lesser)</span>
+<span id="L180" class="LineNr">180 </span><span class="Special">% Reg[0].i = 0x0a0b0c07;</span>
+<span id="L181" class="LineNr">181 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L182" class="LineNr">182 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L183" class="LineNr">183 </span>  <span class="Constant">39</span>  d8                                      <span class="Comment"># compare EBX (reg 3) with EAX (reg 0)</span>
+<span id="L184" class="LineNr">184 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L185" class="LineNr">185 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span>
+<span id="L186" class="LineNr">186 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L187" class="LineNr">187 </span>
+<span id="L188" class="LineNr">188 </span><span class="Delimiter">:(scenario compare_r32_with_r32_equal)</span>
+<span id="L189" class="LineNr">189 </span><span class="Special">% Reg[0].i = 0x0a0b0c0d;</span>
+<span id="L190" class="LineNr">190 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L191" class="LineNr">191 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L192" class="LineNr">192 </span>  <span class="Constant">39</span>  d8                                      <span class="Comment"># compare EBX (reg 3) with EAX (reg 0)</span>
+<span id="L193" class="LineNr">193 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L194" class="LineNr">194 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span>
+<span id="L195" class="LineNr">195 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
 </pre>
 </body>
 </html>
diff --git a/html/subx/012indirect_addressing.cc.html b/html/subx/012indirect_addressing.cc.html
index c6b76529..72211ce3 100644
--- a/html/subx/012indirect_addressing.cc.html
+++ b/html/subx/012indirect_addressing.cc.html
@@ -256,6 +256,86 @@ if ('onhashchange' in window) {
 <span id="L192" class="LineNr">192 </span><span class="traceContains">+run: 'not' of effective address</span>
 <span id="L193" class="LineNr">193 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span>
 <span id="L194" class="LineNr">194 </span><span class="traceContains">+run: storing 0xf0f0ff00</span>
+<span id="L195" class="LineNr">195 </span>
+<span id="L196" class="LineNr">196 </span><span class="SalientComment">//:: compare</span>
+<span id="L197" class="LineNr">197 </span>
+<span id="L198" class="LineNr">198 </span><span class="Delimiter">:(scenario compare_mem_at_r32_with_r32_greater)</span>
+<span id="L199" class="LineNr">199 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L200" class="LineNr">200 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);</span>
+<span id="L201" class="LineNr">201 </span><span class="Special">% Reg[3].i = 0x0a0b0c07;</span>
+<span id="L202" class="LineNr">202 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L203" class="LineNr">203 </span>  <span class="Constant">39</span>  <span class="Constant">18</span>                                      <span class="Comment"># compare EBX (reg 3) with *EAX (reg 0)</span>
+<span id="L204" class="LineNr">204 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L205" class="LineNr">205 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L206" class="LineNr">206 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L207" class="LineNr">207 </span>
+<span id="L208" class="LineNr">208 </span><span class="Delimiter">:(scenario compare_mem_at_r32_with_r32_lesser)</span>
+<span id="L209" class="LineNr">209 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L210" class="LineNr">210 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c07);</span>
+<span id="L211" class="LineNr">211 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L212" class="LineNr">212 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L213" class="LineNr">213 </span>  <span class="Constant">39</span>  <span class="Constant">18</span>                                      <span class="Comment"># compare EBX (reg 3) with *EAX (reg 0)</span>
+<span id="L214" class="LineNr">214 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L215" class="LineNr">215 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L216" class="LineNr">216 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L217" class="LineNr">217 </span>
+<span id="L218" class="LineNr">218 </span><span class="Delimiter">:(scenario compare_mem_at_r32_with_r32_equal)</span>
+<span id="L219" class="LineNr">219 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L220" class="LineNr">220 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);</span>
+<span id="L221" class="LineNr">221 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L222" class="LineNr">222 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L223" class="LineNr">223 </span>  <span class="Constant">39</span>  <span class="Constant">18</span>                                      <span class="Comment"># compare EBX (reg 3) with *EAX (reg 0)</span>
+<span id="L224" class="LineNr">224 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span>
+<span id="L225" class="LineNr">225 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L226" class="LineNr">226 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
+<span id="L227" class="LineNr">227 </span>
+<span id="L228" class="LineNr">228 </span><span class="Comment">//:</span>
+<span id="L229" class="LineNr">229 </span>
+<span id="L230" class="LineNr">230 </span><span class="Delimiter">:(scenario compare_r32_with_mem_at_r32_greater)</span>
+<span id="L231" class="LineNr">231 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L232" class="LineNr">232 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c07);</span>
+<span id="L233" class="LineNr">233 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L234" class="LineNr">234 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L235" class="LineNr">235 </span>  3b  <span class="Constant">18</span>                                      <span class="Comment"># compare *EAX (reg 0) with EBX (reg 3)</span>
+<span id="L236" class="LineNr">236 </span><span class="traceContains">+run: compare effective address with <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L237" class="LineNr">237 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L238" class="LineNr">238 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L239" class="LineNr">239 </span>
+<span id="L240" class="LineNr">240 </span><span class="Delimiter">:(before &quot;End Single-Byte Opcodes&quot;)</span>
+<span id="L241" class="LineNr">241 </span><span class="Normal">case</span> <span class="Constant">0x3b</span>: <span class="Delimiter">{</span>  <span class="Comment">// compare r/m32 with r32</span>
+<span id="L242" class="LineNr">242 </span>  <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L210'>next</a><span class="Delimiter">();</span>
+<span id="L243" class="LineNr">243 </span>  <span class="Normal">uint8_t</span> reg1 = <span class="Delimiter">(</span>modrm&gt;&gt;<span class="Constant">3</span><span class="Delimiter">)</span>&amp;<span class="Constant">0x7</span><span class="Delimiter">;</span>
+<span id="L244" class="LineNr">244 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;compare effective address with <a href='010core.cc.html#L15'>reg</a> &quot;</span> &lt;&lt; <a href='010core.cc.html#L228'>NUM</a><span class="Delimiter">(</span>reg1<span class="Delimiter">)</span> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L245" class="LineNr">245 </span>  <span class="Normal">int32_t</span> arg1 = Reg[reg1]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">;</span>
+<span id="L246" class="LineNr">246 </span>  <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span>
+<span id="L247" class="LineNr">247 </span>  <span class="Normal">int32_t</span> tmp1 = arg1 - *arg2<span class="Delimiter">;</span>
+<span id="L248" class="LineNr">248 </span>  SF = <span class="Delimiter">(</span>tmp1 &lt; <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L249" class="LineNr">249 </span>  <a href='010core.cc.html#L30'>ZF</a> = <span class="Delimiter">(</span>tmp1 == <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L250" class="LineNr">250 </span>  <span class="Normal">int64_t</span> tmp2 = arg1 - *arg2<span class="Delimiter">;</span>
+<span id="L251" class="LineNr">251 </span>  <a href='010core.cc.html#L31'>OF</a> = <span class="Delimiter">(</span>tmp1 != tmp2<span class="Delimiter">);</span>
+<span id="L252" class="LineNr">252 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;SF=&quot;</span> &lt;&lt; SF &lt;&lt; <span class="Constant">&quot;; ZF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L30'>ZF</a> &lt;&lt; <span class="Constant">&quot;; OF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L31'>OF</a> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L253" class="LineNr">253 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
+<span id="L254" class="LineNr">254 </span><span class="Delimiter">}</span>
+<span id="L255" class="LineNr">255 </span>
+<span id="L256" class="LineNr">256 </span><span class="Delimiter">:(scenario compare_r32_with_mem_at_r32_lesser)</span>
+<span id="L257" class="LineNr">257 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L258" class="LineNr">258 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);</span>
+<span id="L259" class="LineNr">259 </span><span class="Special">% Reg[3].i = 0x0a0b0c07;</span>
+<span id="L260" class="LineNr">260 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L261" class="LineNr">261 </span>  3b  <span class="Constant">18</span>                                      <span class="Comment"># compare *EAX (reg 0) with EBX (reg 3)</span>
+<span id="L262" class="LineNr">262 </span><span class="traceContains">+run: compare effective address with <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L263" class="LineNr">263 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L264" class="LineNr">264 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L265" class="LineNr">265 </span>
+<span id="L266" class="LineNr">266 </span><span class="Delimiter">:(scenario compare_r32_with_mem_at_r32_equal)</span>
+<span id="L267" class="LineNr">267 </span><span class="Special">% Reg[0].i = 0x60;</span>
+<span id="L268" class="LineNr">268 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);</span>
+<span id="L269" class="LineNr">269 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span>
+<span id="L270" class="LineNr">270 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L271" class="LineNr">271 </span>  3b  <span class="Constant">18</span>                                      <span class="Comment"># compare *EAX (reg 0) with EBX (reg 3)</span>
+<span id="L272" class="LineNr">272 </span><span class="traceContains">+run: compare effective address with <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L273" class="LineNr">273 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span>
+<span id="L274" class="LineNr">274 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
 </pre>
 </body>
 </html>
diff --git a/html/subx/013immediate_addressing.cc.html b/html/subx/013immediate_addressing.cc.html
index 609c32d3..50164e5e 100644
--- a/html/subx/013immediate_addressing.cc.html
+++ b/html/subx/013immediate_addressing.cc.html
@@ -292,6 +292,109 @@ if ('onhashchange' in window) {
 <span id="L228" class="LineNr">228 </span>  <a href='010core.cc.html#L53'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>^<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span>
 <span id="L229" class="LineNr">229 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
 <span id="L230" class="LineNr">230 </span><span class="Delimiter">}</span>
+<span id="L231" class="LineNr">231 </span>
+<span id="L232" class="LineNr">232 </span><span class="SalientComment">//:: compare</span>
+<span id="L233" class="LineNr">233 </span>
+<span id="L234" class="LineNr">234 </span><span class="Delimiter">:(scenario compare_imm32_with_eax_greater)</span>
+<span id="L235" class="LineNr">235 </span><span class="Special">% Reg[0].i = 0x0d0c0b0a;</span>
+<span id="L236" class="LineNr">236 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L237" class="LineNr">237 </span>  3d                              <span class="PreProc">0</span><span class="Constant">7</span> 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b07 with EAX (reg 0)</span>
+<span id="L238" class="LineNr">238 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a> and <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b07</span>
+<span id="L239" class="LineNr">239 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L240" class="LineNr">240 </span>
+<span id="L241" class="LineNr">241 </span><span class="Delimiter">:(before &quot;End Single-Byte Opcodes&quot;)</span>
+<span id="L242" class="LineNr">242 </span><span class="Normal">case</span> <span class="Constant">0x3d</span>: <span class="Delimiter">{</span>  <span class="Comment">// subtract imm32 from EAX</span>
+<span id="L243" class="LineNr">243 </span>  <span class="Normal">int32_t</span> arg1 = Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">;</span>
+<span id="L244" class="LineNr">244 </span>  <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L215'>imm32</a><span class="Delimiter">();</span>
+<span id="L245" class="LineNr">245 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;compare <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a> and <a href='010core.cc.html#L215'>imm32</a> 0x&quot;</span> &lt;&lt; <a href='010core.cc.html#L226'>HEXWORD</a> &lt;&lt; arg2 &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L246" class="LineNr">246 </span>  <span class="Normal">int32_t</span> tmp1 = arg1 - arg2<span class="Delimiter">;</span>
+<span id="L247" class="LineNr">247 </span>  SF = <span class="Delimiter">(</span>tmp1 &lt; <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L248" class="LineNr">248 </span>  <a href='010core.cc.html#L30'>ZF</a> = <span class="Delimiter">(</span>tmp1 == <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L249" class="LineNr">249 </span>  <span class="Normal">int64_t</span> tmp2 = arg1 - arg2<span class="Delimiter">;</span>
+<span id="L250" class="LineNr">250 </span>  <a href='010core.cc.html#L31'>OF</a> = <span class="Delimiter">(</span>tmp1 != tmp2<span class="Delimiter">);</span>
+<span id="L251" class="LineNr">251 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;SF=&quot;</span> &lt;&lt; SF &lt;&lt; <span class="Constant">&quot;; ZF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L30'>ZF</a> &lt;&lt; <span class="Constant">&quot;; OF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L31'>OF</a> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L252" class="LineNr">252 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
+<span id="L253" class="LineNr">253 </span><span class="Delimiter">}</span>
+<span id="L254" class="LineNr">254 </span>
+<span id="L255" class="LineNr">255 </span><span class="Delimiter">:(scenario compare_imm32_with_eax_lesser)</span>
+<span id="L256" class="LineNr">256 </span><span class="Special">% Reg[0].i = 0x0d0c0b07;</span>
+<span id="L257" class="LineNr">257 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L258" class="LineNr">258 </span>  3d                              0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with EAX (reg 0)</span>
+<span id="L259" class="LineNr">259 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a> and <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a</span>
+<span id="L260" class="LineNr">260 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L261" class="LineNr">261 </span>
+<span id="L262" class="LineNr">262 </span><span class="Delimiter">:(scenario compare_imm32_with_eax_equal)</span>
+<span id="L263" class="LineNr">263 </span><span class="Special">% Reg[0].i = 0x0d0c0b0a;</span>
+<span id="L264" class="LineNr">264 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L265" class="LineNr">265 </span>  3d                              0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with EAX (reg 0)</span>
+<span id="L266" class="LineNr">266 </span><span class="traceContains">+run: compare <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a> and <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a</span>
+<span id="L267" class="LineNr">267 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
+<span id="L268" class="LineNr">268 </span>
+<span id="L269" class="LineNr">269 </span><span class="Comment">//:</span>
+<span id="L270" class="LineNr">270 </span>
+<span id="L271" class="LineNr">271 </span><span class="Delimiter">:(scenario compare_imm32_with_r32_greater)</span>
+<span id="L272" class="LineNr">272 </span><span class="Special">% Reg[3].i = 0x0d0c0b0a;</span>
+<span id="L273" class="LineNr">273 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L274" class="LineNr">274 </span>  <span class="Constant">81</span>  fb                          <span class="PreProc">0</span><span class="Constant">7</span> 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b07 with EBX (reg 3)</span>
+<span id="L275" class="LineNr">275 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b07 with effective address</span>
+<span id="L276" class="LineNr">276 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L277" class="LineNr">277 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L278" class="LineNr">278 </span>
+<span id="L279" class="LineNr">279 </span><span class="Delimiter">:(before &quot;End Op 81 Subops&quot;)</span>
+<span id="L280" class="LineNr">280 </span><span class="Normal">case</span> <span class="Constant">7</span>: <span class="Delimiter">{</span>
+<span id="L281" class="LineNr">281 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;subop compare&quot;</span> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L282" class="LineNr">282 </span>  <span class="Normal">int32_t</span> tmp1 = *arg1 - arg2<span class="Delimiter">;</span>
+<span id="L283" class="LineNr">283 </span>  SF = <span class="Delimiter">(</span>tmp1 &lt; <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L284" class="LineNr">284 </span>  <a href='010core.cc.html#L30'>ZF</a> = <span class="Delimiter">(</span>tmp1 == <span class="Constant">0</span><span class="Delimiter">);</span>
+<span id="L285" class="LineNr">285 </span>  <span class="Normal">int64_t</span> tmp2 = *arg1 - arg2<span class="Delimiter">;</span>
+<span id="L286" class="LineNr">286 </span>  <a href='010core.cc.html#L31'>OF</a> = <span class="Delimiter">(</span>tmp1 != tmp2<span class="Delimiter">);</span>
+<span id="L287" class="LineNr">287 </span>  <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">&quot;run&quot;</span><span class="Delimiter">)</span> &lt;&lt; <span class="Constant">&quot;SF=&quot;</span> &lt;&lt; SF &lt;&lt; <span class="Constant">&quot;; ZF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L30'>ZF</a> &lt;&lt; <span class="Constant">&quot;; OF=&quot;</span> &lt;&lt; <a href='010core.cc.html#L31'>OF</a> &lt;&lt; <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span>
+<span id="L288" class="LineNr">288 </span>  <span class="Identifier">break</span><span class="Delimiter">;</span>
+<span id="L289" class="LineNr">289 </span><span class="Delimiter">}</span>
+<span id="L290" class="LineNr">290 </span>
+<span id="L291" class="LineNr">291 </span><span class="Delimiter">:(scenario compare_imm32_with_r32_lesser)</span>
+<span id="L292" class="LineNr">292 </span><span class="Special">% Reg[3].i = 0x0d0c0b07;</span>
+<span id="L293" class="LineNr">293 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L294" class="LineNr">294 </span>  <span class="Constant">81</span>  fb                          0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with EBX (reg 3)</span>
+<span id="L295" class="LineNr">295 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a with effective address</span>
+<span id="L296" class="LineNr">296 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L297" class="LineNr">297 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L298" class="LineNr">298 </span>
+<span id="L299" class="LineNr">299 </span><span class="Delimiter">:(scenario compare_imm32_with_r32_equal)</span>
+<span id="L300" class="LineNr">300 </span><span class="Special">% Reg[3].i = 0x0d0c0b0a;</span>
+<span id="L301" class="LineNr">301 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L302" class="LineNr">302 </span>  <span class="Constant">81</span>  fb                          0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with EBX (reg 3)</span>
+<span id="L303" class="LineNr">303 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a with effective address</span>
+<span id="L304" class="LineNr">304 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span>
+<span id="L305" class="LineNr">305 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
+<span id="L306" class="LineNr">306 </span>
+<span id="L307" class="LineNr">307 </span><span class="Delimiter">:(scenario compare_imm32_with_mem_at_r32_greater)</span>
+<span id="L308" class="LineNr">308 </span><span class="Special">% Reg[3].i = 0x60;</span>
+<span id="L309" class="LineNr">309 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0d0c0b0a);</span>
+<span id="L310" class="LineNr">310 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L311" class="LineNr">311 </span>  <span class="Constant">81</span>  3b                          <span class="PreProc">0</span><span class="Constant">7</span> 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b07 with *EBX (reg 3)</span>
+<span id="L312" class="LineNr">312 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b07 with effective address</span>
+<span id="L313" class="LineNr">313 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span>
+<span id="L314" class="LineNr">314 </span><span class="traceContains">+run: SF=0; ZF=0; OF=0</span>
+<span id="L315" class="LineNr">315 </span>
+<span id="L316" class="LineNr">316 </span><span class="Delimiter">:(scenario compare_imm32_with_mem_at_r32_lesser)</span>
+<span id="L317" class="LineNr">317 </span><span class="Special">% Reg[3].i = 0x60;</span>
+<span id="L318" class="LineNr">318 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0d0c0b07);</span>
+<span id="L319" class="LineNr">319 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L320" class="LineNr">320 </span>  <span class="Constant">81</span>  3b                          0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with *EBX (reg 3)</span>
+<span id="L321" class="LineNr">321 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a with effective address</span>
+<span id="L322" class="LineNr">322 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span>
+<span id="L323" class="LineNr">323 </span><span class="traceContains">+run: SF=1; ZF=0; OF=0</span>
+<span id="L324" class="LineNr">324 </span>
+<span id="L325" class="LineNr">325 </span><span class="Delimiter">:(scenario compare_imm32_with_mem_at_r32_equal)</span>
+<span id="L326" class="LineNr">326 </span><span class="Special">% Reg[3].i = 0x0d0c0b0a;</span>
+<span id="L327" class="LineNr">327 </span><span class="Special">% Reg[3].i = 0x60;</span>
+<span id="L328" class="LineNr">328 </span><span class="Special">% SET_WORD_IN_MEM(0x60, 0x0d0c0b0a);</span>
+<span id="L329" class="LineNr">329 </span><span class="Comment"># op  ModRM   SIB   displacement  immediate</span>
+<span id="L330" class="LineNr">330 </span>  <span class="Constant">81</span>  3b                          0a 0b 0c 0d  <span class="Comment"># compare 0x0d0c0b0a with *EBX (reg 3)</span>
+<span id="L331" class="LineNr">331 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L215'>imm32</a> 0x0d0c0b0a with effective address</span>
+<span id="L332" class="LineNr">332 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span>
+<span id="L333" class="LineNr">333 </span><span class="traceContains">+run: SF=0; ZF=1; OF=0</span>
 </pre>
 </body>
 </html>
diff --git a/subx/011direct_addressing.cc b/subx/011direct_addressing.cc
index a1d83b8c..facc8378 100644
--- a/subx/011direct_addressing.cc
+++ b/subx/011direct_addressing.cc
@@ -148,3 +148,48 @@ case 0xf7: {  // xor r32 with r/m32
   OF = false;
   break;
 }
+
+//:: compare
+
+:(scenario compare_r32_with_r32_greater)
+% Reg[0].i = 0x0a0b0c0d;
+% Reg[3].i = 0x0a0b0c07;
+# op  ModRM   SIB   displacement  immediate
+  39  d8                                      # compare EBX (reg 3) with EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is reg 0
++run: SF=0; ZF=0; OF=0
+
+:(before "End Single-Byte Opcodes")
+case 0x39: {  // compare r32 with r/m32
+  uint8_t modrm = next();
+  uint8_t reg2 = (modrm>>3)&0x7;
+  trace(2, "run") << "compare reg " << NUM(reg2) << " with effective address" << end();
+  int32_t* arg1 = effective_address(modrm);
+  int32_t arg2 = Reg[reg2].i;
+  int32_t tmp1 = *arg1 - arg2;
+  SF = (tmp1 < 0);
+  ZF = (tmp1 == 0);
+  int64_t tmp2 = *arg1 - arg2;
+  OF = (tmp1 != tmp2);
+  trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end();
+  break;
+}
+
+:(scenario compare_r32_with_r32_lesser)
+% Reg[0].i = 0x0a0b0c07;
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  39  d8                                      # compare EBX (reg 3) with EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is reg 0
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_r32_with_r32_equal)
+% Reg[0].i = 0x0a0b0c0d;
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  39  d8                                      # compare EBX (reg 3) with EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is reg 0
++run: SF=0; ZF=1; OF=0
diff --git a/subx/012indirect_addressing.cc b/subx/012indirect_addressing.cc
index e209d690..38c3d234 100644
--- a/subx/012indirect_addressing.cc
+++ b/subx/012indirect_addressing.cc
@@ -192,3 +192,83 @@ case 0x33: {  // xor r/m32 with r32
 +run: 'not' of effective address
 +run: effective address is mem at address 0x60 (reg 3)
 +run: storing 0xf0f0ff00
+
+//:: compare
+
+:(scenario compare_mem_at_r32_with_r32_greater)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);
+% Reg[3].i = 0x0a0b0c07;
+# op  ModRM   SIB   displacement  immediate
+  39  18                                      # compare EBX (reg 3) with *EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=0; ZF=0; OF=0
+
+:(scenario compare_mem_at_r32_with_r32_lesser)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c07);
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  39  18                                      # compare EBX (reg 3) with *EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_mem_at_r32_with_r32_equal)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  39  18                                      # compare EBX (reg 3) with *EAX (reg 0)
++run: compare reg 3 with effective address
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=0; ZF=1; OF=0
+
+//:
+
+:(scenario compare_r32_with_mem_at_r32_greater)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c07);
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  3b  18                                      # compare *EAX (reg 0) with EBX (reg 3)
++run: compare effective address with reg 3
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=0; ZF=0; OF=0
+
+:(before "End Single-Byte Opcodes")
+case 0x3b: {  // compare r/m32 with r32
+  uint8_t modrm = next();
+  uint8_t reg1 = (modrm>>3)&0x7;
+  trace(2, "run") << "compare effective address with reg " << NUM(reg1) << end();
+  int32_t arg1 = Reg[reg1].i;
+  int32_t* arg2 = effective_address(modrm);
+  int32_t tmp1 = arg1 - *arg2;
+  SF = (tmp1 < 0);
+  ZF = (tmp1 == 0);
+  int64_t tmp2 = arg1 - *arg2;
+  OF = (tmp1 != tmp2);
+  trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end();
+  break;
+}
+
+:(scenario compare_r32_with_mem_at_r32_lesser)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);
+% Reg[3].i = 0x0a0b0c07;
+# op  ModRM   SIB   displacement  immediate
+  3b  18                                      # compare *EAX (reg 0) with EBX (reg 3)
++run: compare effective address with reg 3
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_r32_with_mem_at_r32_equal)
+% Reg[0].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0a0b0c0d);
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  3b  18                                      # compare *EAX (reg 0) with EBX (reg 3)
++run: compare effective address with reg 3
++run: effective address is mem at address 0x60 (reg 0)
++run: SF=0; ZF=1; OF=0
diff --git a/subx/013immediate_addressing.cc b/subx/013immediate_addressing.cc
index ff08dea5..c370217a 100644
--- a/subx/013immediate_addressing.cc
+++ b/subx/013immediate_addressing.cc
@@ -228,3 +228,106 @@ case 6: {
   BINARY_BITWISE_OP(^, *arg1, arg2);
   break;
 }
+
+//:: compare
+
+:(scenario compare_imm32_with_eax_greater)
+% Reg[0].i = 0x0d0c0b0a;
+# op  ModRM   SIB   displacement  immediate
+  3d                              07 0b 0c 0d  # compare 0x0d0c0b07 with EAX (reg 0)
++run: compare reg EAX and imm32 0x0d0c0b07
++run: SF=0; ZF=0; OF=0
+
+:(before "End Single-Byte Opcodes")
+case 0x3d: {  // subtract imm32 from EAX
+  int32_t arg1 = Reg[EAX].i;
+  int32_t arg2 = imm32();
+  trace(2, "run") << "compare reg EAX and imm32 0x" << HEXWORD << arg2 << end();
+  int32_t tmp1 = arg1 - arg2;
+  SF = (tmp1 < 0);
+  ZF = (tmp1 == 0);
+  int64_t tmp2 = arg1 - arg2;
+  OF = (tmp1 != tmp2);
+  trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end();
+  break;
+}
+
+:(scenario compare_imm32_with_eax_lesser)
+% Reg[0].i = 0x0d0c0b07;
+# op  ModRM   SIB   displacement  immediate
+  3d                              0a 0b 0c 0d  # compare 0x0d0c0b0a with EAX (reg 0)
++run: compare reg EAX and imm32 0x0d0c0b0a
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_imm32_with_eax_equal)
+% Reg[0].i = 0x0d0c0b0a;
+# op  ModRM   SIB   displacement  immediate
+  3d                              0a 0b 0c 0d  # compare 0x0d0c0b0a with EAX (reg 0)
++run: compare reg EAX and imm32 0x0d0c0b0a
++run: SF=0; ZF=1; OF=0
+
+//:
+
+:(scenario compare_imm32_with_r32_greater)
+% Reg[3].i = 0x0d0c0b0a;
+# op  ModRM   SIB   displacement  immediate
+  81  fb                          07 0b 0c 0d  # compare 0x0d0c0b07 with EBX (reg 3)
++run: combine imm32 0x0d0c0b07 with effective address
++run: effective address is reg 3
++run: SF=0; ZF=0; OF=0
+
+:(before "End Op 81 Subops")
+case 7: {
+  trace(2, "run") << "subop compare" << end();
+  int32_t tmp1 = *arg1 - arg2;
+  SF = (tmp1 < 0);
+  ZF = (tmp1 == 0);
+  int64_t tmp2 = *arg1 - arg2;
+  OF = (tmp1 != tmp2);
+  trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end();
+  break;
+}
+
+:(scenario compare_imm32_with_r32_lesser)
+% Reg[3].i = 0x0d0c0b07;
+# op  ModRM   SIB   displacement  immediate
+  81  fb                          0a 0b 0c 0d  # compare 0x0d0c0b0a with EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is reg 3
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_imm32_with_r32_equal)
+% Reg[3].i = 0x0d0c0b0a;
+# op  ModRM   SIB   displacement  immediate
+  81  fb                          0a 0b 0c 0d  # compare 0x0d0c0b0a with EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is reg 3
++run: SF=0; ZF=1; OF=0
+
+:(scenario compare_imm32_with_mem_at_r32_greater)
+% Reg[3].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0d0c0b0a);
+# op  ModRM   SIB   displacement  immediate
+  81  3b                          07 0b 0c 0d  # compare 0x0d0c0b07 with *EBX (reg 3)
++run: combine imm32 0x0d0c0b07 with effective address
++run: effective address is mem at address 0x60 (reg 3)
++run: SF=0; ZF=0; OF=0
+
+:(scenario compare_imm32_with_mem_at_r32_lesser)
+% Reg[3].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0d0c0b07);
+# op  ModRM   SIB   displacement  immediate
+  81  3b                          0a 0b 0c 0d  # compare 0x0d0c0b0a with *EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is mem at address 0x60 (reg 3)
++run: SF=1; ZF=0; OF=0
+
+:(scenario compare_imm32_with_mem_at_r32_equal)
+% Reg[3].i = 0x0d0c0b0a;
+% Reg[3].i = 0x60;
+% SET_WORD_IN_MEM(0x60, 0x0d0c0b0a);
+# op  ModRM   SIB   displacement  immediate
+  81  3b                          0a 0b 0c 0d  # compare 0x0d0c0b0a with *EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is mem at address 0x60 (reg 3)
++run: SF=0; ZF=1; OF=0