4055

subx: Implement 'and' for the addressing modes we've built so far.

3 files changed, 105 insertions, 0 deletions

diff --git a/subx/011direct_addressing.cc b/subx/011direct_addressing.cc
index 8d280784..de5e923a 100644
--- a/subx/011direct_addressing.cc
+++ b/subx/011direct_addressing.cc
@@ -62,3 +62,24 @@ case 0x29: {  // subtract r32 from r/m32
   BINARY_ARITHMETIC_OP(-, *arg1, Reg[arg2].i);
   break;
 }
+
+//:: and
+
+:(scenario and_r32_with_r32)
+% Reg[0].i = 0x0a0b0c0d;
+% Reg[3].i = 0x000000ff;
+# op  ModR/M  SIB   displacement  immediate
+  21  d8                                      # and EBX (reg 3) with destination EAX (reg 0)
++run: and reg 3 with effective address
++run: effective address is reg 0
++run: storing 0x0000000d
+
+:(before "End Single-Byte Opcodes")
+case 0x21: {  // and r32 with r/m32
+  uint8_t modrm = next();
+  uint8_t arg2 = (modrm>>3)&0x7;
+  trace(2, "run") << "and reg " << NUM(arg2) << " with effective address" << end();
+  int32_t* arg1 = effective_address(modrm);
+  BINARY_BITWISE_OP(&, *arg1, Reg[arg2].u);
+  break;
+}
diff --git a/subx/012indirect_addressing.cc b/subx/012indirect_addressing.cc
index f9aafda5..6e9a5f01 100644
--- a/subx/012indirect_addressing.cc
+++ b/subx/012indirect_addressing.cc
@@ -79,3 +79,40 @@ case 0x2b: {  // subtract r/m32 from r32
   BINARY_ARITHMETIC_OP(-, Reg[arg1].i, *arg2);
   break;
 }
+
+//:: and
+
+:(scenario and_r32_with_mem_at_r32)
+% Reg[0].i = 0x60;
+% Mem.at(0x60) = 0x0d;
+% Mem.at(0x61) = 0x0c;
+% Mem.at(0x62) = 0x0b;
+% Mem.at(0x63) = 0x0a;
+% Reg[3].i = 0xff;
+# op  ModRM   SIB   displacement  immediate
+  21  18                                      # and EBX (reg 3) with *EAX (reg 0)
++run: and reg 3 with effective address
++run: effective address is mem at address 0x60 (reg 0)
++run: storing 0x0000000d
+
+//:
+
+:(scenario and_mem_at_r32_with_r32)
+% Reg[0].i = 0x60;
+% Mem.at(0x60) = 0xff;
+% Reg[3].i = 0x0a0b0c0d;
+# op  ModRM   SIB   displacement  immediate
+  23  18                                      # and *EAX (reg 0) with EBX (reg 3)
++run: and effective address with reg 3
++run: effective address is mem at address 0x60 (reg 0)
++run: storing 0x0000000d
+
+:(before "End Single-Byte Opcodes")
+case 0x23: {  // and r/m32 with r32
+  uint8_t modrm = next();
+  uint8_t arg1 = (modrm>>3)&0x7;
+  trace(2, "run") << "and effective address with reg " << NUM(arg1) << end();
+  const int32_t* arg2 = effective_address(modrm);
+  BINARY_BITWISE_OP(&, Reg[arg1].u, *arg2);
+  break;
+}
diff --git a/subx/013immediate_addressing.cc b/subx/013immediate_addressing.cc
index c995bd90..8fe39279 100644
--- a/subx/013immediate_addressing.cc
+++ b/subx/013immediate_addressing.cc
@@ -87,3 +87,50 @@ case 5: {
   BINARY_ARITHMETIC_OP(-, *arg1, arg2);
   break;
 }
+
+//:: and
+
+:(scenario and_imm32_with_eax)
+% Reg[EAX].i = 0xff;
+# op  ModR/M  SIB   displacement  immediate
+  25                              0a 0b 0c 0d  # and 0x0d0c0b0a with EAX (reg 0)
++run: and imm32 0x0d0c0b0a with reg EAX
++run: storing 0x0000000a
+
+:(before "End Single-Byte Opcodes")
+case 0x25: {  // and imm32 with EAX
+  int32_t arg2 = imm32();
+  trace(2, "run") << "and imm32 0x" << HEXWORD << arg2 << " with reg EAX" << end();
+  BINARY_BITWISE_OP(&, Reg[EAX].i, arg2);
+  break;
+}
+
+//:
+
+:(scenario and_imm32_with_mem_at_r32)
+% Reg[3].i = 0x60;
+% Mem.at(0x60) = 0xff;
+# op  ModRM   SIB   displacement  immediate
+  81  23                          0a 0b 0c 0d  # and 0x0d0c0b0a with *EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is mem at address 0x60 (reg 3)
++run: subop and
++run: storing 0x0000000a
+
+//:
+
+:(scenario and_imm32_with_r32)
+% Reg[3].i = 0xff;
+# op  ModRM   SIB   displacement  immediate
+  81  e3                          0a 0b 0c 0d  # and 0x0d0c0b0a with EBX (reg 3)
++run: combine imm32 0x0d0c0b0a with effective address
++run: effective address is reg 3
++run: subop and
++run: storing 0x0000000a
+
+:(before "End Op 81 Subops")
+case 4: {
+  trace(2, "run") << "subop and" << end();
+  BINARY_BITWISE_OP(&, *arg1, arg2);
+  break;
+}