4037

Fix non-standard switch statement.

2 files changed, 15 insertions, 12 deletions

diff --git a/subx/010core.cc b/subx/010core.cc
index a1d61ba8..eba8e00d 100644
--- a/subx/010core.cc
+++ b/subx/010core.cc
@@ -98,10 +98,10 @@ void run(const string& text_bytes) {
 void run_one_instruction() {
   uint8_t op=0, op2=0, op3=0;
   switch (op = next()) {
-  // our first opcode
   case 0xf4:  // hlt
     EIP = End_of_program;
     break;
+  // our first opcode
   case 0x05: {  // add imm32 to EAX
     int32_t arg2 = imm32();
     trace(2, "run") << "add imm32 0x" << HEXWORD << arg2 << " to reg EAX" << end();
diff --git a/subx/011add.cc b/subx/011add.cc
index 4f504be6..5ba1e080 100644
--- a/subx/011add.cc
+++ b/subx/011add.cc
@@ -29,18 +29,21 @@ int32_t* effective_address(uint8_t modrm) {
   uint8_t rm = modrm & 0x7;
   int32_t* result = 0;
   switch (mod) {
-    case 0:
-      // mod 0 is usually indirect addressing
-      switch (rm) {
-      default:
-        trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
-        assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
-        result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u));  // rely on the host itself being in little-endian order
-        break;
-      // End Mod 0 Special-Cases
-      }
+  case 0:
+    // mod 0 is usually indirect addressing
+    switch (rm) {
+    default:
+      trace(99, "run") << "effective address is mem at address 0x" << std::hex << Reg[rm].u << " (reg " << static_cast<int>(rm) << ")" << end();
+      assert(Reg[rm].u + sizeof(int32_t) <= Mem.size());
+      result = reinterpret_cast<int32_t*>(&Mem.at(Reg[rm].u));  // rely on the host itself being in little-endian order
       break;
-    // End Mod Special-Cases
+    // End Mod 0 Special-Cases
+    }
+    break;
+  // End Mod Special-Cases
+  default:
+    cerr << "unrecognized mod bits: " << static_cast<int>(mod) << '\n';
+    exit(1);
   }
   return result;
 }