From 836d13dbc92c97cf529d6a51972be350e8ee1b2c Mon Sep 17 00:00:00 2001 From: "Kartik K. Agaram" Date: Wed, 24 Jan 2018 00:50:28 -0800 Subject: 4182 - subx: beginnings of support for indexed addressing --- subx/014index_addressing.cc | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 subx/014index_addressing.cc diff --git a/subx/014index_addressing.cc b/subx/014index_addressing.cc new file mode 100644 index 00000000..1615e652 --- /dev/null +++ b/subx/014index_addressing.cc @@ -0,0 +1,45 @@ +//: operating on memory at the address provided by some register plus optional scale and offset + +:(scenario add_r32_to_mem_at_r32_with_sib) +% Reg[3].i = 0x10; +% Reg[0].i = 0x60; +% SET_WORD_IN_MEM(0x60, 1); +# op ModR/M SIB displacement immediate + 01 1c 20 # add EBX (reg 3) to *EAX (reg 0) +# SIB in binary: 00 (scale 1) 100 (no index) 000 (base EAX) +# See Table 2-3 of the Intel programming manual. ++run: add reg 3 to effective address ++run: effective address is mem at address 0x60 (reg 0) ++run: storing 0x00000011 + +:(before "End Mod 0 Special-cases") +case 4: + // exception: SIB addressing + uint8_t sib = next(); + uint8_t base = sib&0x7; + uint8_t index = (sib>>3)&0x7; + if (index == ESP) { + // ignore index and scale + trace(2, "run") << "effective address is mem at address 0x" << std::hex << Reg[base].u << " (reg " << NUM(base) << ")" << end(); + result = reinterpret_cast(&Mem.at(Reg[base].u)); + } + else { + uint8_t scale = (1 << (sib>>6)); + uint32_t addr = Reg[base].u + Reg[index].u*scale; + trace(2, "run") << "effective address is mem at address 0x" << std::hex << addr << " (reg " << NUM(base) << " + reg " << NUM(index) << " * " << NUM(scale) << ")" << end(); + result = reinterpret_cast(&Mem.at(addr)); + } + break; + +:(scenario add_r32_to_mem_at_base_plus_index) +% Reg[3].i = 0x10; // source +% Reg[0].i = 0x5e; // dest base +% Reg[1].i = 0x2; // dest index +% SET_WORD_IN_MEM(0x60, 1); +# op ModR/M SIB displacement immediate + 01 1c 08 # add EBX (reg 3) to *(EAX+ECX) +# SIB in binary: 00 (scale 1) 001 (index ECX) 000 (base EAX) +# See Table 2-3 of the Intel programming manual. ++run: add reg 3 to effective address ++run: effective address is mem at address 0x60 (reg 0 + reg 1 * 1) ++run: storing 0x00000011 -- cgit 1.4.1-2-gfad0 /td>

path: root/edit/Readme.md

blob: 698e534b11f6471a5ff04fb1d13f75e0884157fa (plain) (blame)