From cb4be511b7bae326802420125403ba91870f30c5 Mon Sep 17 00:00:00 2001 From: "Kartik K. Agaram" Date: Wed, 18 Oct 2017 01:53:25 -0700 Subject: 4081 --- html/subx/013immediate_addressing.cc.html | 440 +++++++++++++++--------------- subx/013immediate_addressing.cc | 28 +- 2 files changed, 230 insertions(+), 238 deletions(-) diff --git a/html/subx/013immediate_addressing.cc.html b/html/subx/013immediate_addressing.cc.html index adaff3e0..6215b01c 100644 --- a/html/subx/013immediate_addressing.cc.html +++ b/html/subx/013immediate_addressing.cc.html @@ -228,230 +228,226 @@ if ('onhashchange' in window) { 164 +run: subop or 165 +run: storing 0xddccbbaa 166 -167 //: -168 -169 :(scenario or_imm32_with_r32) -170 % Reg[3].i = 0xd0c0b0a0; -171 # op ModRM SIB displacement immediate -172 81 cb 0a 0b 0c 0d # or 0x0d0c0b0a with EBX (reg 3) -173 +run: combine imm32 0x0d0c0b0a with effective address -174 +run: effective address is reg 3 -175 +run: subop or -176 +run: storing 0xddccbbaa -177 -178 :(before "End Op 81 Subops") -179 case 1: { -180 trace(2, "run") << "subop or" << end(); -181 BINARY_BITWISE_OP(|, *arg1, arg2); -182 break; -183 } +167 :(before "End Op 81 Subops") +168 case 1: { +169 trace(2, "run") << "subop or" << end(); +170 BINARY_BITWISE_OP(|, *arg1, arg2); +171 break; +172 } +173 +174 :(scenario or_imm32_with_r32) +175 % Reg[3].i = 0xd0c0b0a0; +176 # op ModRM SIB displacement immediate +177 81 cb 0a 0b 0c 0d # or 0x0d0c0b0a with EBX (reg 3) +178 +run: combine imm32 0x0d0c0b0a with effective address +179 +run: effective address is reg 3 +180 +run: subop or +181 +run: storing 0xddccbbaa +182 +183 //:: xor 184 -185 //:: xor -186 -187 :(scenario xor_imm32_with_eax) -188 % Reg[EAX].i = 0xddccb0a0; -189 # op ModR/M SIB displacement immediate -190 35 0a 0b 0c 0d # xor 0x0d0c0b0a with EAX (reg 0) -191 +run: xor imm32 0x0d0c0b0a with reg EAX -192 +run: storing 0xd0c0bbaa -193 -194 :(before "End Single-Byte Opcodes") -195 case 0x35: { // xor imm32 with EAX -196 int32_t arg2 = imm32(); -197 trace(2, "run") << "xor imm32 0x" << HEXWORD << arg2 << " with reg EAX" << end(); -198 BINARY_BITWISE_OP(^, Reg[EAX].i, arg2); -199 break; -200 } +185 :(scenario xor_imm32_with_eax) +186 % Reg[EAX].i = 0xddccb0a0; +187 # op ModR/M SIB displacement immediate +188 35 0a 0b 0c 0d # xor 0x0d0c0b0a with EAX (reg 0) +189 +run: xor imm32 0x0d0c0b0a with reg EAX +190 +run: storing 0xd0c0bbaa +191 +192 :(before "End Single-Byte Opcodes") +193 case 0x35: { // xor imm32 with EAX +194 int32_t arg2 = imm32(); +195 trace(2, "run") << "xor imm32 0x" << HEXWORD << arg2 << " with reg EAX" << end(); +196 BINARY_BITWISE_OP(^, Reg[EAX].i, arg2); +197 break; +198 } +199 +200 //: 201 -202 //: -203 -204 :(scenario xor_imm32_with_mem_at_r32) -205 % Reg[3].i = 0x60; -206 % SET_WORD_IN_MEM(0x60, 0xd0c0b0a0); -207 # op ModRM SIB displacement immediate -208 81 33 0a 0b 0c 0d # xor 0x0d0c0b0a with *EBX (reg 3) -209 +run: combine imm32 0x0d0c0b0a with effective address -210 +run: effective address is mem at address 0x60 (reg 3) -211 +run: subop xor -212 +run: storing 0xddccbbaa -213 -214 //: -215 -216 :(scenario xor_imm32_with_r32) -217 % Reg[3].i = 0xd0c0b0a0; -218 # op ModRM SIB displacement immediate -219 81 f3 0a 0b 0c 0d # xor 0x0d0c0b0a with EBX (reg 3) -220 +run: combine imm32 0x0d0c0b0a with effective address -221 +run: effective address is reg 3 -222 +run: subop xor -223 +run: storing 0xddccbbaa -224 -225 :(before "End Op 81 Subops") -226 case 6: { -227 trace(2, "run") << "subop xor" << end(); -228 BINARY_BITWISE_OP(^, *arg1, arg2); -229 break; -230 } -231 -232 //:: compare (cmp) -233 -234 :(scenario compare_imm32_with_eax_greater) -235 % Reg[0].i = 0x0d0c0b0a; -236 # op ModRM SIB displacement immediate -237 3d 07 0b 0c 0d # compare 0x0d0c0b07 with EAX (reg 0) -238 +run: compare reg EAX and imm32 0x0d0c0b07 -239 +run: SF=0; ZF=0; OF=0 -240 -241 :(before "End Single-Byte Opcodes") -242 case 0x3d: { // subtract imm32 from EAX -243 int32_t arg1 = Reg[EAX].i; -244 int32_t arg2 = imm32(); -245 trace(2, "run") << "compare reg EAX and imm32 0x" << HEXWORD << arg2 << end(); -246 int32_t tmp1 = arg1 - arg2; -247 SF = (tmp1 < 0); -248 ZF = (tmp1 == 0); -249 int64_t tmp2 = arg1 - arg2; -250 OF = (tmp1 != tmp2); -251 trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end(); -252 break; -253 } -254 -255 :(scenario compare_imm32_with_eax_lesser) -256 % Reg[0].i = 0x0d0c0b07; -257 # op ModRM SIB displacement immediate -258 3d 0a 0b 0c 0d # compare 0x0d0c0b0a with EAX (reg 0) -259 +run: compare reg EAX and imm32 0x0d0c0b0a -260 +run: SF=1; ZF=0; OF=0 -261 -262 :(scenario compare_imm32_with_eax_equal) -263 % Reg[0].i = 0x0d0c0b0a; -264 # op ModRM SIB displacement immediate -265 3d 0a 0b 0c 0d # compare 0x0d0c0b0a with EAX (reg 0) -266 +run: compare reg EAX and imm32 0x0d0c0b0a -267 +run: SF=0; ZF=1; OF=0 -268 -269 //: -270 -271 :(scenario compare_imm32_with_r32_greater) -272 % Reg[3].i = 0x0d0c0b0a; -273 # op ModRM SIB displacement immediate -274 81 fb 07 0b 0c 0d # compare 0x0d0c0b07 with EBX (reg 3) -275 +run: combine imm32 0x0d0c0b07 with effective address -276 +run: effective address is reg 3 -277 +run: SF=0; ZF=0; OF=0 -278 -279 :(before "End Op 81 Subops") -280 case 7: { -281 trace(2, "run") << "subop compare" << end(); -282 int32_t tmp1 = *arg1 - arg2; -283 SF = (tmp1 < 0); -284 ZF = (tmp1 == 0); -285 int64_t tmp2 = *arg1 - arg2; -286 OF = (tmp1 != tmp2); -287 trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end(); -288 break; -289 } -290 -291 :(scenario compare_imm32_with_r32_lesser) -292 % Reg[3].i = 0x0d0c0b07; -293 # op ModRM SIB displacement immediate -294 81 fb 0a 0b 0c 0d # compare 0x0d0c0b0a with EBX (reg 3) -295 +run: combine imm32 0x0d0c0b0a with effective address -296 +run: effective address is reg 3 -297 +run: SF=1; ZF=0; OF=0 -298 -299 :(scenario compare_imm32_with_r32_equal) -300 % Reg[3].i = 0x0d0c0b0a; -301 # op ModRM SIB displacement immediate -302 81 fb 0a 0b 0c 0d # compare 0x0d0c0b0a with EBX (reg 3) -303 +run: combine imm32 0x0d0c0b0a with effective address -304 +run: effective address is reg 3 -305 +run: SF=0; ZF=1; OF=0 -306 -307 :(scenario compare_imm32_with_mem_at_r32_greater) -308 % Reg[3].i = 0x60; -309 % SET_WORD_IN_MEM(0x60, 0x0d0c0b0a); -310 # op ModRM SIB displacement immediate -311 81 3b 07 0b 0c 0d # compare 0x0d0c0b07 with *EBX (reg 3) -312 +run: combine imm32 0x0d0c0b07 with effective address -313 +run: effective address is mem at address 0x60 (reg 3) -314 +run: SF=0; ZF=0; OF=0 -315 -316 :(scenario compare_imm32_with_mem_at_r32_lesser) -317 % Reg[3].i = 0x60; -318 % SET_WORD_IN_MEM(0x60, 0x0d0c0b07); -319 # op ModRM SIB displacement immediate -320 81 3b 0a 0b 0c 0d # compare 0x0d0c0b0a with *EBX (reg 3) -321 +run: combine imm32 0x0d0c0b0a with effective address -322 +run: effective address is mem at address 0x60 (reg 3) -323 +run: SF=1; ZF=0; OF=0 -324 -325 :(scenario compare_imm32_with_mem_at_r32_equal) -326 % Reg[3].i = 0x0d0c0b0a; -327 % Reg[3].i = 0x60; -328 % SET_WORD_IN_MEM(0x60, 0x0d0c0b0a); -329 # op ModRM SIB displacement immediate -330 81 3b 0a 0b 0c 0d # compare 0x0d0c0b0a with *EBX (reg 3) -331 +run: combine imm32 0x0d0c0b0a with effective address -332 +run: effective address is mem at address 0x60 (reg 3) -333 +run: SF=0; ZF=1; OF=0 -334 -335 //:: copy (mov) -336 -337 :(scenario copy_imm32_to_r32) -338 # op ModRM SIB displacement immediate -339 b8 03 0a 0b 0c 0d # copy 0x0d0c0b0a to EBX (reg 3) -340 +run: copy imm32 0x0d0c0b0a to reg 3 -341 -342 :(before "End Single-Byte Opcodes") -343 case 0xb8: { // copy imm32 to r32 -344 uint8_t modrm = next(); -345 int32_t arg2 = imm32(); -346 uint8_t reg1 = modrm&0x7; // ignore mod bits -347 trace(2, "run") << "copy imm32 0x" << HEXWORD << arg2 << " to reg " << NUM(reg1) << end(); -348 Reg[reg1].i = arg2; -349 break; -350 } -351 -352 //: -353 -354 :(scenario copy_imm32_to_mem_at_r32) -355 % Reg[3].i = 0x60; -356 # op ModRM SIB displacement immediate -357 c7 03 0a 0b 0c 0d # copy 0x0d0c0b0a to *EBX (reg 3) -358 +run: copy imm32 0x0d0c0b0a to effective address -359 +run: effective address is mem at address 0x60 (reg 3) -360 -361 :(before "End Single-Byte Opcodes") -362 case 0xc7: { // copy imm32 to r32 -363 uint8_t modrm = next(); -364 int32_t arg2 = imm32(); -365 trace(2, "run") << "copy imm32 0x" << HEXWORD << arg2 << " to effective address" << end(); -366 int32_t* arg1 = effective_address(modrm); -367 *arg1 = arg2; -368 break; -369 } -370 -371 //:: push -372 -373 :(scenario push_imm32) -374 % Reg[ESP].u = 0x14; -375 # op ModRM SIB displacement immediate -376 68 af 00 00 00 # push *EAX (reg 0) to stack -377 +run: push imm32 0x000000af -378 +run: ESP is now 0x00000010 -379 +run: contents at ESP: 0x000000af -380 -381 :(before "End Single-Byte Opcodes") -382 case 0x68: { -383 int32_t val = imm32(); -384 trace(2, "run") << "push imm32 0x" << HEXWORD << val << end(); -385 Reg[ESP].u -= 4; -386 *reinterpret_cast<uint32_t*>(&Mem.at(Reg[ESP].u)) = val; -387 trace(2, "run") << "ESP is now 0x" << HEXWORD << Reg[ESP].u << end(); -388 trace(2, "run") << "contents at ESP: 0x" << HEXWORD << *reinterpret_cast<uint32_t*>(&Mem.at(Reg[ESP].u)) << end(); -389 break; -390 } +202 :(scenario xor_imm32_with_mem_at_r32) +203 % Reg[3].i = 0x60; +204 % SET_WORD_IN_MEM(0x60, 0xd0c0b0a0); +205 # op ModRM SIB displacement immediate +206 81 33 0a 0b 0c 0d # xor 0x0d0c0b0a with *EBX (reg 3) +207 +run: combine imm32 0x0d0c0b0a with effective address +208 +run: effective address is mem at address 0x60 (reg 3) +209 +run: subop xor +210 +run: storing 0xddccbbaa +211 +212 :(before "End Op 81 Subops") +213 case 6: { +214 trace(2, "run") << "subop xor" << end(); +215 BINARY_BITWISE_OP(^, *arg1, arg2); +216 break; +217 } +218 +219 :(scenario xor_imm32_with_r32) +220 % Reg[3].i = 0xd0c0b0a0; +221 # op ModRM SIB displacement immediate +222 81 f3 0a 0b 0c 0d # xor 0x0d0c0b0a with EBX (reg 3) +223 +run: combine imm32 0x0d0c0b0a with effective address +224 +run: effective address is reg 3 +225 +run: subop xor +226 +run: storing 0xddccbbaa +227 +228 //:: compare (cmp) +229 +230 :(scenario compare_imm32_with_eax_greater) +231 % Reg[0].i = 0x0d0c0b0a; +232 # op ModRM SIB displacement immediate +233 3d 07 0b 0c 0d # compare 0x0d0c0b07 with EAX (reg 0) +234 +run: compare reg EAX and imm32 0x0d0c0b07 +235 +run: SF=0; ZF=0; OF=0 +236 +237 :(before "End Single-Byte Opcodes") +238 case 0x3d: { // subtract imm32 from EAX +239 int32_t arg1 = Reg[EAX].i; +240 int32_t arg2 = imm32(); +241 trace(2, "run") << "compare reg EAX and imm32 0x" << HEXWORD << arg2 << end(); +242 int32_t tmp1 = arg1 - arg2; +243 SF = (tmp1 < 0); +244 ZF = (tmp1 == 0); +245 int64_t tmp2 = arg1 - arg2; +246 OF = (tmp1 != tmp2); +247 trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end(); +248 break; +249 } +250 +251 :(scenario compare_imm32_with_eax_lesser) +252 % Reg[0].i = 0x0d0c0b07; +253 # op ModRM SIB displacement immediate +254 3d 0a 0b 0c 0d # compare 0x0d0c0b0a with EAX (reg 0) +255 +run: compare reg EAX and imm32 0x0d0c0b0a +256 +run: SF=1; ZF=0; OF=0 +257 +258 :(scenario compare_imm32_with_eax_equal) +259 % Reg[0].i = 0x0d0c0b0a; +260 # op ModRM SIB displacement immediate +261 3d 0a 0b 0c 0d # compare 0x0d0c0b0a with EAX (reg 0) +262 +run: compare reg EAX and imm32 0x0d0c0b0a +263 +run: SF=0; ZF=1; OF=0 +264 +265 //: +266 +267 :(scenario compare_imm32_with_r32_greater) +268 % Reg[3].i = 0x0d0c0b0a; +269 # op ModRM SIB displacement immediate +270 81 fb 07 0b 0c 0d # compare 0x0d0c0b07 with EBX (reg 3) +271 +run: combine imm32 0x0d0c0b07 with effective address +272 +run: effective address is reg 3 +273 +run: SF=0; ZF=0; OF=0 +274 +275 :(before "End Op 81 Subops") +276 case 7: { +277 trace(2, "run") << "subop compare" << end(); +278 int32_t tmp1 = *arg1 - arg2; +279 SF = (tmp1 < 0); +280 ZF = (tmp1 == 0); +281 int64_t tmp2 = *arg1 - arg2; +282 OF = (tmp1 != tmp2); +283 trace(2, "run") << "SF=" << SF << "; ZF=" << ZF << "; OF=" << OF << end(); +284 break; +285 } +286 +287 :(scenario compare_imm32_with_r32_lesser) +288 % Reg[3].i = 0x0d0c0b07; +289 # op ModRM SIB displacement immediate +290 81 fb 0a 0b 0c 0d # compare 0x0d0c0b0a with EBX (reg 3) +291 +run: combine imm32 0x0d0c0b0a with effective address +292 +run: effective address is reg 3 +293 +run: SF=1; ZF=0; OF=0 +294 +295 :(scenario compare_imm32_with_r32_equal) +296 % Reg[3].i = 0x0d0c0b0a; +297 # op ModRM SIB displacement immediate +298 81 fb 0a 0b 0c 0d # compare 0x0d0c0b0a with EBX (reg 3) +299 +run: combine imm32 0x0d0c0b0a with effective address +300 +run: effective address is reg 3 +301 +run: SF=0; ZF=1; OF=0 +302 +303 :(scenario compare_imm32_with_mem_at_r32_greater) +304 % Reg[3].i = 0x60; +305 % SET_WORD_IN_MEM(0x60, 0x0d0c0b0a); +306 # op ModRM SIB displacement immediate +307 81 3b 07 0b 0c 0d # compare 0x0d0c0b07 with *EBX (reg 3) +308 +run: combine imm32 0x0d0c0b07 with effective address +309 +run: effective address is mem at address 0x60 (reg 3) +310 +run: SF=0; ZF=0; OF=0 +311 +312 :(scenario compare_imm32_with_mem_at_r32_lesser) +313 % Reg[3].i = 0x60; +314 % SET_WORD_IN_MEM(0x60, 0x0d0c0b07); +315 # op ModRM SIB displacement immediate +316 81 3b 0a 0b 0c 0d # compare 0x0d0c0b0a with *EBX (reg 3) +317 +run: combine imm32 0x0d0c0b0a with effective address +318 +run: effective address is mem at address 0x60 (reg 3) +319 +run: SF=1; ZF=0; OF=0 +320 +321 :(scenario compare_imm32_with_mem_at_r32_equal) +322 % Reg[3].i = 0x0d0c0b0a; +323 % Reg[3].i = 0x60; +324 % SET_WORD_IN_MEM(0x60, 0x0d0c0b0a); +325 # op ModRM SIB displacement immediate +326 81 3b 0a 0b 0c 0d # compare 0x0d0c0b0a with *EBX (reg 3) +327 +run: combine imm32 0x0d0c0b0a with effective address +328 +run: effective address is mem at address 0x60 (reg 3) +329 +run: SF=0; ZF=1; OF=0 +330 +331 //:: copy (mov) +332 +333 :(scenario copy_imm32_to_r32) +334 # op ModRM SIB displacement immediate +335 b8 03 0a 0b 0c 0d # copy 0x0d0c0b0a to EBX (reg 3) +336 +run: copy imm32 0x0d0c0b0a to reg 3 +337 +338 :(before "End Single-Byte Opcodes") +339 case 0xb8: { // copy imm32 to r32 +340 uint8_t modrm = next(); +341 int32_t arg2 = imm32(); +342 uint8_t reg1 = modrm&0x7; // ignore mod bits +343 trace(2, "run") << "copy imm32 0x" << HEXWORD << arg2 << " to reg " << NUM(reg1) << end(); +344 Reg[reg1].i = arg2; +345 break; +346 } +347 +348 //: +349 +350 :(scenario copy_imm32_to_mem_at_r32) +351 % Reg[3].i = 0x60; +352 # op ModRM SIB displacement immediate +353 c7 03 0a 0b 0c 0d # copy 0x0d0c0b0a to *EBX (reg 3) +354 +run: copy imm32 0x0d0c0b0a to effective address +355 +run: effective address is mem at address 0x60 (reg 3) +356 +357 :(before "End Single-Byte Opcodes") +358 case 0xc7: { // copy imm32 to r32 +359 uint8_t modrm = next(); +360 int32_t arg2 = imm32(); +361 trace(2, "run") << "copy imm32 0x" << HEXWORD << arg2 << " to effective address" << end(); +362 int32_t* arg1 = effective_address(modrm); +363 *arg1 = arg2; +364 break; +365 } +366 +367 //:: push +368 +369 :(scenario push_imm32) +370 % Reg[ESP].u = 0x14; +371 # op ModRM SIB displacement immediate +372 68 af 00 00 00 # push *EAX (reg 0) to stack +373 +run: push imm32 0x000000af +374 +run: ESP is now 0x00000010 +375 +run: contents at ESP: 0x000000af +376 +377 :(before "End Single-Byte Opcodes") +378 case 0x68: { +379 int32_t val = imm32(); +380 trace(2, "run") << "push imm32 0x" << HEXWORD << val << end(); +381 Reg[ESP].u -= 4; +382 *reinterpret_cast<uint32_t*>(&Mem.at(Reg[ESP].u)) = val; +383 trace(2, "run") << "ESP is now 0x" << HEXWORD << Reg[ESP].u << end(); +384 trace(2, "run") << "contents at ESP: 0x" << HEXWORD << *reinterpret_cast<uint32_t*>(&Mem.at(Reg[ESP].u)) << end(); +385 break; +386 } diff --git a/subx/013immediate_addressing.cc b/subx/013immediate_addressing.cc index 2e4b459a..14121d42 100644 --- a/subx/013immediate_addressing.cc +++ b/subx/013immediate_addressing.cc @@ -164,7 +164,12 @@ case 0x0d: { // or imm32 with EAX +run: subop or +run: storing 0xddccbbaa -//: +:(before "End Op 81 Subops") +case 1: { + trace(2, "run") << "subop or" << end(); + BINARY_BITWISE_OP(|, *arg1, arg2); + break; +} :(scenario or_imm32_with_r32) % Reg[3].i = 0xd0c0b0a0; @@ -175,13 +180,6 @@ case 0x0d: { // or imm32 with EAX +run: subop or +run: storing 0xddccbbaa -:(before "End Op 81 Subops") -case 1: { - trace(2, "run") << "subop or" << end(); - BINARY_BITWISE_OP(|, *arg1, arg2); - break; -} - //:: xor :(scenario xor_imm32_with_eax) @@ -211,7 +209,12 @@ case 0x35: { // xor imm32 with EAX +run: subop xor +run: storing 0xddccbbaa -//: +:(before "End Op 81 Subops") +case 6: { + trace(2, "run") << "subop xor" << end(); + BINARY_BITWISE_OP(^, *arg1, arg2); + break; +} :(scenario xor_imm32_with_r32) % Reg[3].i = 0xd0c0b0a0; @@ -222,13 +225,6 @@ case 0x35: { // xor imm32 with EAX +run: subop xor +run: storing 0xddccbbaa -:(before "End Op 81 Subops") -case 6: { - trace(2, "run") << "subop xor" << end(); - BINARY_BITWISE_OP(^, *arg1, arg2); - break; -} - //:: compare (cmp) :(scenario compare_imm32_with_eax_greater) -- cgit 1.4.1-2-gfad0 d=839dc88dc0439ae3f32c8c0f7650f32b09f311cc'>839dc88d ^ 
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