From f13576b5d273ef9175e938b15f55bb1ead22fb1d Mon Sep 17 00:00:00 2001 From: Kartik Agaram Date: Mon, 5 Oct 2020 10:16:53 -0700 Subject: 6957 The final fix to the raytracing program involves rounding modes. It turns out x86 processors round floats by default, unlike C which has trained me to expect truncation. Rather than mess with the MXCSR register, I added another instruction for truncation. Now milestone 3 emits perfectly correct results. --- mu_instructions | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'mu_instructions') diff --git a/mu_instructions b/mu_instructions index 9e7f26bc..f93bb685 100644 --- a/mu_instructions +++ b/mu_instructions @@ -327,10 +327,19 @@ var/xreg <- convert var2/reg2 => "f3 0f 2a/convert-to-float %" reg2 " " xreg var/xreg <- convert var2 => "f3 0f 2a/convert-to-float *(ebp+" var2.stack-offset ") " xreg "/x32" var/xreg <- convert *var2/reg2 => "f3 0f 2a/convert-to-float *" reg2 " " xreg "/x32" +Converting floats to ints performs rounding by default. (We don't mess with the +MXCSR control register.) + var/reg <- convert var2/xreg2 => "f3 0f 2d/convert-to-int %" xreg2 " " reg "/r32" var/reg <- convert var2 => "f3 0f 2d/convert-to-int *(ebp+" var2.stack-offset ") " reg "/r32" var/reg <- convert *var2/reg2 => "f3 0f 2d/convert-to-int *" reg2 " " reg "/r32" +There's a separate instruction for truncating the fractional part. + +var/reg <- truncate var2/xreg2 => "f3 0f 2c/truncate-to-int %" xreg2 " " reg "/r32" +var/reg <- truncate var2 => "f3 0f 2c/truncate-to-int *(ebp+" var2.stack-offset ") " reg "/r32" +var/reg <- truncate *var2/reg2 => "f3 0f 2c/truncate-to-int *" reg2 " " reg "/r32" + There are no instructions accepting floating-point literals. To obtain integer literals in floating-point registers, copy them to general-purpose registers and then convert them to floating-point. -- cgit 1.4.1-2-gfad0