1 //: Since we're tagging operands with their types, let's start checking these
  2 //: operand types for each instruction.
  3 
  4 void test_check_missing_imm8_operand() {
  5   Hide_errors = true;
  6   run(
  7       "== code 0x1\n"
  8       "cd\n"  // interrupt ??
  9   );
 10   CHECK_TRACE_CONTENTS(
 11       "error: 'cd' (software interrupt): missing imm8 operand\n"
 12   );
 13 }
 14 
 15 :(before "Pack Operands(segment code)")
 16 check_operands(code);
 17 if (trace_contains_errors()) return;
 18 
 19 :(code)
 20 void check_operands(const segment& code) {
 21   trace(3, "transform") << "-- check operands" << end();
 22   for (int i = 0;  i < SIZE(code.lines);  ++i) {
 23     check_operands(code.lines.at(i));
 24     if (trace_contains_errors()) return;  // stop at the first mal-formed instruction
 25   }
 26 }
 27 
 28 void check_operands(const line& inst) {
 29   word op = preprocess_op(inst.words.at(0));
 30   if (op.data == "0f") {
 31     check_operands_0f(inst);
 32     return;
 33   }
 34   if (op.data == "f3") {
 35     check_operands_f3(inst);
 36     return;
 37   }
 38   check_operands(inst, op);
 39 }
 40 
 41 word preprocess_op(word/*copy*/ op) {
 42   op.data = tolower(op.data.c_str());
 43   // opcodes can't be negative
 44   if (starts_with(op.data, "0x"))
 45     op.data = op.data.substr(2);
 46   if (SIZE(op.data) == 1)
 47     op.data = string("0")+op.data;
 48   return op;
 49 }
 50 
 51 void test_preprocess_op() {
 52   word w1;  w1.data = "0xf";
 53   word w2;  w2.data = "0f";
 54   CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
 55 }
 56 
 57 //: To check the operands for an opcode, we'll track the permitted operands
 58 //: for each supported opcode in a bitvector. That way we can often compute the
 59 //: 'received' operand bitvector for each instruction's operands and compare
 60 //: it with the 'expected' bitvector.
 61 //:
 62 //: The 'expected' and 'received' bitvectors can be different; the MODRM bit
 63 //: in the 'expected' bitvector maps to multiple 'received' operand types in
 64 //: an instruction. We deal in expected bitvectors throughout.
 65 
 66 :(before "End Types")
 67 enum expected_operand_type {
 68   // start from the least significant bit
 69   MODRM,  // more complex, may also involve disp8 or disp32
 70   SUBOP,
 71   DISP8,
 72   DISP16,
 73   DISP32,
 74   IMM8,
 75   IMM32,
 76   NUM_OPERAND_TYPES
 77 };
 78 :(before "End Globals")
 79 vector<string> Operand_type_name;
 80 map<string, expected_operand_type> Operand_type;
 81 :(before "End One-time Setup")
 82 init_op_types();
 83 :(code)
 84 void init_op_types() {
 85   assert(NUM_OPERAND_TYPES <= /*bits in a uint8_t*/8);
 86   Operand_type_name.resize(NUM_OPERAND_TYPES);
 87   #define DEF(type) Operand_type_name.at(type) = tolower(#type), put(Operand_type, tolower(#type), type);
 88   DEF(MODRM);
 89   DEF(SUBOP);
 90   DEF(DISP8);
 91   DEF(DISP16);
 92   DEF(DISP32);
 93   DEF(IMM8);
 94   DEF(IMM32);
 95   #undef DEF
 96 }
 97 
 98 :(before "End Globals")
 99 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands;
100 const uint8_t INVALID_OPERANDS = 0xff;  // no instruction uses all the operand types
101 :(before "End One-time Setup")
102 init_permitted_operands();
103 :(code)
104 void init_permitted_operands() {
105   //// Class A: just op, no operands
106   // halt
107   put(Permitted_operands, "f4", 0x00);
108   // inc
109   put(Permitted_operands, "40", 0x00);
110   put(Permitted_operands, "41", 0x00);
111   put(Permitted_operands, "42", 0x00);
112   put(Permitted_operands, "43", 0x00);
113   put(Permitted_operands, "44", 0x00);
114   put(Permitted_operands, "45", 0x00);
115   put(Permitted_operands, "46", 0x00);
116   put(Permitted_operands, "47", 0x00);
117   // dec
118   put(Permitted_operands, "48", 0x00);
119   put(Permitted_operands, "49", 0x00);
120   put(Permitted_operands, "4a", 0x00);
121   put(Permitted_operands, "4b", 0x00);
122   put(Permitted_operands, "4c", 0x00);
123   put(Permitted_operands, "4d", 0x00);
124   put(Permitted_operands, "4e", 0x00);
125   put(Permitted_operands, "4f", 0x00);
126   // push
127   put(Permitted_operands, "50", 0x00);
128   put(Permitted_operands, "51", 0x00);
129   put(Permitted_operands, "52", 0x00);
130   put(Permitted_operands, "53", 0x00);
131   put(Permitted_operands, "54", 0x00);
132   put(Permitted_operands, "55", 0x00);
133   put(Permitted_operands, "56", 0x00);
134   put(Permitted_operands, "57", 0x00);
135   // pop
136   put(Permitted_operands, "58", 0x00);
137   put(Permitted_operands, "59", 0x00);
138   put(Permitted_operands, "5a", 0x00);
139   put(Permitted_operands, "5b", 0x00);
140   put(Permitted_operands, "5c", 0x00);
141   put(Permitted_operands, "5d", 0x00);
142   put(Permitted_operands, "5e", 0x00);
143   put(Permitted_operands, "5f", 0x00);
144   // sign-extend EAX into EDX
145   put(Permitted_operands, "99", 0x00);
146   // return
147   put(Permitted_operands, "c3", 0x00);
148 
149   //// Class B: just op and disp8
150   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
151   //  0     0     0      |0       1     0     0
152 
153   // jump
154   put(Permitted_operands, "eb", 0x04);
155   put(Permitted_operands, "72", 0x04);
156   put(Permitted_operands, "73", 0x04);
157   put(Permitted_operands, "74", 0x04);
158   put(Permitted_operands, "75", 0x04);
159   put(Permitted_operands, "76", 0x04);
160   put(Permitted_operands, "77", 0x04);
161   put(Permitted_operands, "7c", 0x04);
162   put(Permitted_operands, "7d", 0x04);
163   put(Permitted_operands, "7e", 0x04);
164   put(Permitted_operands, "7f", 0x04);
165 
166   //// Class D: just op and disp32
167   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
168   //  0     0     1      |0       0     0     0
169   put(Permitted_operands, "e8", 0x10);  // call
170   put(Permitted_operands, "e9", 0x10);  // jump
171 
172   //// Class E: just op and imm8
173   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
174   //  0     1     0      |0       0     0     0
175   put(Permitted_operands, "cd", 0x20);  // software interrupt
176 
177   //// Class F: just op and imm32
178   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
179   //  1     0     0      |0       0     0     0
180   put(Permitted_operands, "05", 0x40);  // add
181   put(Permitted_operands, "2d", 0x40);  // subtract
182   put(Permitted_operands, "25", 0x40);  // and
183   put(Permitted_operands, "0d", 0x40);  // or
184   put(Permitted_operands, "35", 0x40);  // xor
185   put(Permitted_operands, "3d", 0x40);  // compare
186   put(Permitted_operands, "68", 0x40);  // push
187   // copy
188   put(Permitted_operands, "b8", 0x40);
189   put(Permitted_operands, "b9", 0x40);
190   put(Permitted_operands, "ba", 0x40);
191   put(Permitted_operands, "bb", 0x40);
192   put(Permitted_operands, "bc", 0x40);
193   put(Permitted_operands, "bd", 0x40);
194   put(Permitted_operands, "be", 0x40);
195   put(Permitted_operands, "bf", 0x40);
196 
197   //// Class M: using ModR/M byte
198   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
199   //  0     0     0      |0       0     0     1
200 
201   // add
202   put(Permitted_operands, "01", 0x01);
203   put(Permitted_operands, "03", 0x01);
204   // subtract
205   put(Permitted_operands, "29", 0x01);
206   put(Permitted_operands, "2b", 0x01);
207   // and
208   put(Permitted_operands, "21", 0x01);
209   put(Permitted_operands, "23", 0x01);
210   // or
211   put(Permitted_operands, "09", 0x01);
212   put(Permitted_operands, "0b", 0x01);
213   // xor
214   put(Permitted_operands, "31", 0x01);
215   put(Permitted_operands, "33", 0x01);
216   // compare
217   put(Permitted_operands, "39", 0x01);
218   put(Permitted_operands, "3b", 0x01);
219   // copy
220   put(Permitted_operands, "88", 0x01);
221   put(Permitted_operands, "89", 0x01);
222   put(Permitted_operands, "8a", 0x01);
223   put(Permitted_operands, "8b", 0x01);
224   // swap
225   put(Permitted_operands, "87", 0x01);
226   // copy address (lea)
227   put(Permitted_operands, "8d", 0x01);
228 
229   //// Class N: op, ModR/M and subop (not r32)
230   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
231   //  0     0     0      |0       0     1     1
232   put(Permitted_operands, "8f", 0x03);  // pop
233   put(Permitted_operands, "d3", 0x03);  // shift
234   put(Permitted_operands, "f7", 0x03);  // test/not/mul/div
235   put(Permitted_operands, "ff", 0x03);  // jump/push/call
236 
237   //// Class O: op, ModR/M, subop (not r32) and imm8
238   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
239   //  0     1     0      |0       0     1     1
240   put(Permitted_operands, "c1", 0x23);  // combine
241   put(Permitted_operands, "c6", 0x23);  // copy
242 
243   //// Class P: op, ModR/M, subop (not r32) and imm32
244   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
245   //  1     0     0      |0       0     1     1
246   put(Permitted_operands, "81", 0x43);  // combine
247   put(Permitted_operands, "c7", 0x43);  // copy
248 
249   //// Class Q: op, ModR/M and imm32
250   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
251   //  1     0     0      |0       0     0     1
252   put(Permitted_operands, "69", 0x41);  // multiply
253 
254   // End Init Permitted Operands
255 }
256 
257 #define HAS(bitvector, bit)  ((bitvector) & (1 << (bit)))
258 #define SET(bitvector, bit)  ((bitvector) | (1 << (bit)))
259 #define CLEAR(bitvector, bit)  ((bitvector) & (~(1 << (bit))))
260 
261 void check_operands(const line& inst, const word& op) {
262   if (!is_hex_byte(op)) return;
263   uint8_t expected_bitvector = get(Permitted_operands, op.data);
264   if (HAS(expected_bitvector, MODRM)) {
265     check_operands_modrm(inst, op);
266     compare_bitvector_modrm(inst, expected_bitvector, maybe_name(op));
267   }
268   else {
269     compare_bitvector(inst, expected_bitvector, maybe_name(op));
270   }
271 }
272 
273 //: Many instructions can be checked just by comparing bitvectors.
274 
275 void compare_bitvector(const line& inst, uint8_t expected, const string& maybe_op_name) {
276   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
277   uint8_t bitvector = compute_expected_operand_bitvector(inst);
278   if (trace_contains_errors()) return;  // duplicate operand type
279   if (bitvector == expected) return;  // all good with this instruction
280   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
281 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
282     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
283     const string& optype = Operand_type_name.at(i);
284     if ((bitvector & 0x1) > (expected & 0x1))
285       raise << "'" << to_string(inst) << "'" << maybe_op_name << ": unexpected " << optype << " operand\n" << end();
286     else
287       raise << "'" << to_string(inst) << "'" << maybe_op_name << ": missing " << optype << " operand\n" << end();
288     // continue giving all errors for a single instruction
289   }
290   // ignore settings in any unused bits
291 }
292 
293 string maybe_name(const word& op) {
294   if (!is_hex_byte(op)) return "";
295   if (!contains_key(Name, op.data)) return "";
296   // strip stuff in parens from the name
297   const string& s = get(Name, op.data);
298   return " ("+s.substr(0, s.find(" ("))+')';
299 }
300 
301 uint32_t compute_expected_operand_bitvector(const line& inst) {
302   set<string> operands_found;
303   uint32_t bitvector = 0;
304   for (int i = /*skip op*/1;  i < SIZE(inst.words);  ++i) {
305     bitvector = bitvector | expected_bit_for_received_operand(inst.words.at(i), operands_found, inst);
306     if (trace_contains_errors()) return INVALID_OPERANDS;  // duplicate operand type
307   }
308   return bitvector;
309 }
310 
311 bool has_operands(const line& inst) {
312   return SIZE(inst.words) > first_operand(inst);
313 }
314 
315 int first_operand(const line& inst) {
316   if (inst.words.at(0).data == "0f") return 2;
317   if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
318     if (inst.words.at(1).data == "0f")
319       return 3;
320     else
321       return 2;
322   }
323   return 1;
324 }
325 
326 // Scan the metadata of 'w' and return the expected bit corresponding to any operand type.
327 // Also raise an error if metadata contains multiple operand types.
328 uint32_t expected_bit_for_received_operand(const word& w, set<string>& instruction_operands, const line& inst) {
329   uint32_t bv = 0;
330   bool found = false;
331   for (int i = 0;  i < SIZE(w.metadata);  ++i) {
332     string/*copy*/ curr = w.metadata.at(i);
333     string expected_metadata = curr;
334     if (curr == "mod" || curr == "rm32" || curr == "r32" || curr == "scale" || curr == "index" || curr == "base")
335       expected_metadata = "modrm";
336     else if (!contains_key(Operand_type, curr)) continue;  // ignore unrecognized metadata
337     if (found) {
338       raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
339       return INVALID_OPERANDS;
340     }
341     if (instruction_operands.find(curr) != instruction_operands.end()) {
342       raise << "'" << to_string(inst) << "': duplicate " << curr << " operand\n" << end();
343       return INVALID_OPERANDS;
344     }
345     instruction_operands.insert(curr);
346     bv = (1 << get(Operand_type, expected_metadata));
347     found = true;
348   }
349   return bv;
350 }
351 
352 void test_conflicting_operand_type() {
353   Hide_errors = true;
354   run(
355       "== code 0x1\n"
356       "cd/software-interrupt 80/imm8/imm32\n"
357   );
358   CHECK_TRACE_CONTENTS(
359       "error: '80/imm8/imm32' has conflicting operand types; it should have only one\n"
360   );
361 }
362 
363 //: Instructions computing effective addresses have more complex rules, so
364 //: we'll hard-code a common set of instruction-decoding rules.
365 
366 void test_check_missing_mod_operand() {
367   Hide_errors = true;
368   run(
369       "== code 0x1\n"
370       "81 0/add/subop       3/rm32/ebx 1/imm32\n"
371   );
372   CHECK_TRACE_CONTENTS(
373       "error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand\n"
374   );
375 }
376 
377 void check_operands_modrm(const line& inst, const word& op) {
378   if (all_hex_bytes(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
379   check_operand_metadata_present(inst, "mod", op);
380   check_operand_metadata_present(inst, "rm32", op);
381   // no check for r32; some instructions don't use it; just assume it's 0 if missing
382   if (op.data == "81" || op.data == "8f" || op.data == "ff") {  // keep sync'd with 'help subop'
383     check_operand_metadata_present(inst, "subop", op);
384     check_operand_metadata_absent(inst, "r32", op, "should be replaced by subop");
385   }
386   if (trace_contains_errors()) return;
387   if (metadata(inst, "rm32").data != "4") return;
388   // SIB byte checks
389   uint8_t mod = hex_byte(metadata(inst, "mod").data);
390   if (mod != /*direct*/3) {
391     check_operand_metadata_present(inst, "base", op);
392     check_operand_metadata_present(inst, "index", op);  // otherwise why go to SIB?
393   }
394   else {
395     check_operand_metadata_absent(inst, "base", op, "direct mode");
396     check_operand_metadata_absent(inst, "index", op, "direct mode");
397   }
398   // no check for scale; 0 (2**0 = 1) by default
399 }
400 
401 // same as compare_bitvector, with one additional exception for modrm-based
402 // instructions: they may use an extra displacement on occasion
403 void compare_bitvector_modrm(const line& inst, uint8_t expected, const string& maybe_op_name) {
404   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
405   uint8_t bitvector = compute_expected_operand_bitvector(inst);
406   if (trace_contains_errors()) return;  // duplicate operand type
407   // update 'expected' bitvector for the additional exception
408   if (has_operand_metadata(inst, "mod")) {
409     int32_t mod = parse_int(metadata(inst, "mod").data);
410     switch (mod) {
411     case 0:
412       if (has_operand_metadata(inst, "rm32") && parse_int(metadata(inst, "rm32").data) == 5)
413         expected |= (1<<DISP32);
414       break;
415     case 1:
416       expected |= (1<<DISP8);
417       break;
418     case 2:
419       expected |= (1<<DISP32);
420       break;
421     }
422   }
423   if (bitvector == expected) return;  // all good with this instruction
424   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
425 //?     cerr << "comparing for modrm " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
426     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
427     const string& optype = Operand_type_name.at(i);
428     if ((bitvector & 0x1) > (expected & 0x1))
429       raise << "'" << to_string(inst) << "'" << maybe_op_name << ": unexpected " << optype << " operand\n" << end();
430     else
431       raise << "'" << to_string(inst) << "'" << maybe_op_name << ": missing " << optype << " operand\n" << end();
432     // continue giving all errors for a single instruction
433   }
434   // ignore settings in any unused bits
435 }
436 
437 void check_operand_metadata_present(const line& inst, const string& type, const word& op) {
438   if (!has_operand_metadata(inst, type))
439     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << type << " operand\n" << end();
440 }
441 
442 void check_operand_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
443   if (has_operand_metadata(inst, type))
444     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << type << " operand (" << msg << ")\n" << end();
445 }
446 
447 void test_modrm_with_displacement() {
448   Reg[EAX].u = 0x1;
449   transform(
450       "== code 0x1\n"
451       // just avoid null pointer
452       "8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8\n"  // copy *(EAX+4) to EDX
453   );
454   CHECK_TRACE_COUNT("error", 0);
455 }
456 
457 void test_check_missing_disp8() {
458   Hide_errors = true;
459   transform(
460       "== code 0x1\n"
461       "89/copy 1/mod/lookup+disp8 0/rm32/EAX 1/r32/ECX\n"  // missing disp8
462   );
463   CHECK_TRACE_CONTENTS(
464       "error: '89/copy 1/mod/lookup+disp8 0/rm32/EAX 1/r32/ECX' (copy r32 to rm32): missing disp8 operand\n"
465   );
466 }
467 
468 void test_check_missing_disp32() {
469   Hide_errors = true;
470   transform(
471       "== code 0x1\n"
472       "8b/copy 0/mod/indirect 5/rm32/.disp32 2/r32/EDX\n"  // missing disp32
473   );
474   CHECK_TRACE_CONTENTS(
475       "error: '8b/copy 0/mod/indirect 5/rm32/.disp32 2/r32/EDX' (copy rm32 to r32): missing disp32 operand\n"
476   );
477 }
478 
479 void test_conflicting_operands_in_modrm_instruction() {
480   Hide_errors = true;
481   run(
482       "== code 0x1\n"
483       "01/add 0/mod 3/mod\n"
484   );
485   CHECK_TRACE_CONTENTS(
486       "error: '01/add 0/mod 3/mod' has conflicting mod operands\n"
487   );
488 }
489 
490 void test_conflicting_operand_type_modrm() {
491   Hide_errors = true;
492   run(
493       "== code 0x1\n"
494       "01/add 0/mod 3/rm32/r32\n"
495   );
496   CHECK_TRACE_CONTENTS(
497       "error: '3/rm32/r32' has conflicting operand types; it should have only one\n"
498   );
499 }
500 
501 void test_check_missing_rm32_operand() {
502   Hide_errors = true;
503   run(
504       "== code 0x1\n"
505       "81 0/add/subop 0/mod            1/imm32\n"
506   );
507   CHECK_TRACE_CONTENTS(
508       "error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand\n"
509   );
510 }
511 
512 void test_check_missing_subop_operand() {
513   Hide_errors = true;
514   run(
515       "== code 0x1\n"
516       "81             0/mod 3/rm32/ebx 1/imm32\n"
517   );
518   CHECK_TRACE_CONTENTS(
519       "error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand\n"
520   );
521 }
522 
523 void test_check_missing_base_operand() {
524   Hide_errors = true;
525   run(
526       "== code 0x1\n"
527       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32\n"
528   );
529   CHECK_TRACE_CONTENTS(
530       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand\n"
531   );
532 }
533 
534 void test_check_missing_index_operand() {
535   Hide_errors = true;
536   run(
537       "== code 0x1\n"
538       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32\n"
539   );
540   CHECK_TRACE_CONTENTS(
541       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand\n"
542   );
543 }
544 
545 void test_check_missing_base_operand_2() {
546   Hide_errors = true;
547   run(
548       "== code 0x1\n"
549       "81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32\n"
550   );
551   CHECK_TRACE_CONTENTS(
552       "error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand\n"
553   );
554 }
555 
556 void test_check_extra_displacement() {
557   Hide_errors = true;
558   run(
559       "== code 0x1\n"
560       "89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8\n"
561   );
562   CHECK_TRACE_CONTENTS(
563       "error: '89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8' (copy r32 to rm32): unexpected disp8 operand\n"
564   );
565 }
566 
567 void test_check_duplicate_operand() {
568   Hide_errors = true;
569   run(
570       "== code 0x1\n"
571       "89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 1/r32\n"
572   );
573   CHECK_TRACE_CONTENTS(
574       "error: '89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 1/r32': duplicate r32 operand\n"
575   );
576 }
577 
578 void test_check_base_operand_not_needed_in_direct_mode() {
579   run(
580       "== code 0x1\n"
581       "81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32\n"
582   );
583   CHECK_TRACE_COUNT("error", 0);
584 }
585 
586 void test_extra_modrm() {
587   Hide_errors = true;
588   run(
589       "== code 0x1\n"
590       "59/pop-to-ECX  3/mod/direct 1/rm32/ECX 4/r32/ESP\n"
591   );
592   CHECK_TRACE_CONTENTS(
593       "error: '59/pop-to-ECX 3/mod/direct 1/rm32/ECX 4/r32/ESP' (pop top of stack to ECX): unexpected modrm operand\n"
594   );
595 }
596 
597 //:: similarly handle multi-byte opcodes
598 
599 void check_operands_0f(const line& inst) {
600   assert(inst.words.at(0).data == "0f");
601   if (SIZE(inst.words) == 1) {
602     raise << "opcode '0f' requires a second opcode\n" << end();
603     return;
604   }
605   word op = preprocess_op(inst.words.at(1));
606   if (!contains_key(Name_0f, op.data)) {
607     raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
608     return;
609   }
610   check_operands_0f(inst, op);
611 }
612 
613 void check_operands_f3(const line& /*unused*/) {
614   raise << "no supported opcodes starting with f3\n" << end();
615 }
616 
617 void test_check_missing_disp32_operand() {
618   Hide_errors = true;
619   run(
620       "== code 0x1\n"
621       "  0f 84  # jmp if ZF to ??\n"
622   );
623   CHECK_TRACE_CONTENTS(
624       "error: '0f 84' (jump disp32 bytes away if equal, if ZF is set): missing disp32 operand\n"
625   );
626 }
627 
628 void test_0f_opcode_with_modrm() {
629   transform(
630       "== code 0x1\n"
631       "0f af/multiply 2/mod/*+disp32 5/rm32/ebp 8/disp32 0/r32\n"
632   );
633   CHECK_TRACE_DOESNT_CONTAIN_ERRORS();
634 }
635 
636 :(before "End Globals")
637 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands_0f;
638 :(before "End Init Permitted Operands")
639 //// Class D: just op and disp32
640 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
641 //  0     0     1      |0       0     0     0
642 put_new(Permitted_operands_0f, "82", 0x10);
643 put_new(Permitted_operands_0f, "83", 0x10);
644 put_new(Permitted_operands_0f, "84", 0x10);
645 put_new(Permitted_operands_0f, "85", 0x10);
646 put_new(Permitted_operands_0f, "86", 0x10);
647 put_new(Permitted_operands_0f, "87", 0x10);
648 put_new(Permitted_operands_0f, "8c", 0x10);
649 put_new(Permitted_operands_0f, "8d", 0x10);
650 put_new(Permitted_operands_0f, "8e", 0x10);
651 put_new(Permitted_operands_0f, "8f", 0x10);
652 
653 //// Class M: using ModR/M byte
654 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
655 //  0     0     0      |0       0     0     1
656 put_new(Permitted_operands_0f, "af", 0x01);
657 // setcc
658 put_new(Permitted_operands_0f, "92", 0x01);
659 put_new(Permitted_operands_0f, "93", 0x01);
660 put_new(Permitted_operands_0f, "94", 0x01);
661 put_new(Permitted_operands_0f, "95", 0x01);
662 put_new(Permitted_operands_0f, "96", 0x01);
663 put_new(Permitted_operands_0f, "97", 0x01);
664 put_new(Permitted_operands_0f, "9c", 0x01);
665 put_new(Permitted_operands_0f, "9d", 0x01);
666 put_new(Permitted_operands_0f, "9e", 0x01);
667 put_new(Permitted_operands_0f, "9f", 0x01);
668 
669 :(code)
670 void check_operands_0f(const line& inst, const word& op) {
671   uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
672   if (HAS(expected_bitvector, MODRM)) {
673     check_operands_modrm(inst, op);
674     compare_bitvector_modrm(inst, expected_bitvector, maybe_name_0f(op));
675   }
676   else {
677     compare_bitvector(inst, CLEAR(expected_bitvector, MODRM), maybe_name_0f(op));
678   }
679 }
680 
681 string maybe_name_0f(const word& op) {
682   if (!is_hex_byte(op)) return "";
683   if (!contains_key(Name_0f, op.data)) return "";
684   // strip stuff in parens from the name
685   const string& s = get(Name_0f, op.data);
686   return " ("+s.substr(0, s.find(" ("))+')';
687 }
688 
689 string tolower(const char* s) {
690   ostringstream out;
691   for (/*nada*/;  *s;  ++s)
692     out << static_cast<char>(tolower(*s));
693   return out.str();
694 }
695 
696 #undef HAS
697 #undef SET
698 #undef CLEAR
699 
700 :(before "End Includes")
701 #include<cctype>