1 //: Since we're tagging operands with their types, let's start checking these
  2 //: operand types for each instruction.
  3 
  4 :(scenario check_missing_imm8_operand)
  5 % Hide_errors = true;
  6 == 0x1
  7 cd  # int ??
  8 +error: 'cd' (software interrupt): missing imm8 operand
  9 
 10 :(before "Pack Operands(segment code)")
 11 check_operands(code);
 12 if (trace_contains_errors()) return;
 13 
 14 :(code)
 15 void check_operands(const segment& code) {
 16   trace(99, "transform") << "-- check operands" << end();
 17   for (int i = 0;  i < SIZE(code.lines);  ++i) {
 18     check_operands(code.lines.at(i));
 19     if (trace_contains_errors()) return;  // stop at the first mal-formed instruction
 20   }
 21 }
 22 
 23 void check_operands(const line& inst) {
 24   word op = preprocess_op(inst.words.at(0));
 25   if (op.data == "0f") {
 26     check_operands_0f(inst);
 27     return;
 28   }
 29   if (op.data == "f3") {
 30     check_operands_f3(inst);
 31     return;
 32   }
 33   check_operands(inst, op);
 34 }
 35 
 36 word preprocess_op(word/*copy*/ op) {
 37   op.data = tolower(op.data.c_str());
 38   // opcodes can't be negative
 39   if (starts_with(op.data, "0x"))
 40     op.data = op.data.substr(2);
 41   if (SIZE(op.data) == 1)
 42     op.data = string("0")+op.data;
 43   return op;
 44 }
 45 
 46 void test_preprocess_op() {
 47   word w1;  w1.data = "0xf";
 48   word w2;  w2.data = "0f";
 49   CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
 50 }
 51 
 52 //: To check the operands for an opcode, we'll track the permitted operands
 53 //: for each supported opcode in a bitvector. That way we can often compute the
 54 //: 'received' operand bitvector for each instruction's operands and compare
 55 //: it with the 'expected' bitvector.
 56 //:
 57 //: The 'expected' and 'received' bitvectors can be different; the MODRM bit
 58 //: in the 'expected' bitvector maps to multiple 'received' operand types in
 59 //: an instruction. We deal in expected bitvectors throughout.
 60 
 61 :(before "End Types")
 62 enum expected_operand_type {
 63   // start from the least significant bit
 64   MODRM,  // more complex, may also involve disp8 or disp32
 65   SUBOP,
 66   DISP8,
 67   DISP16,
 68   DISP32,
 69   IMM8,
 70   IMM32,
 71   NUM_OPERAND_TYPES
 72 };
 73 :(before "End Globals")
 74 vector<string> Operand_type_name;
 75 map<string, expected_operand_type> Operand_type;
 76 :(before "End One-time Setup")
 77 init_op_types();
 78 :(code)
 79 void init_op_types() {
 80   assert(NUM_OPERAND_TYPES <= /*bits in a uint8_t*/8);
 81   Operand_type_name.resize(NUM_OPERAND_TYPES);
 82   #define DEF(type) Operand_type_name.at(type) = tolower(#type), put(Operand_type, tolower(#type), type);
 83   DEF(MODRM);
 84   DEF(SUBOP);
 85   DEF(DISP8);
 86   DEF(DISP16);
 87   DEF(DISP32);
 88   DEF(IMM8);
 89   DEF(IMM32);
 90   #undef DEF
 91 }
 92 
 93 :(before "End Globals")
 94 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands;
 95 const uint8_t INVALID_OPERANDS = 0xff;  // no instruction uses all the operand types
 96 :(before "End One-time Setup")
 97 init_permitted_operands();
 98 :(code)
 99 void init_permitted_operands() {
100   //// Class A: just op, no operands
101   // halt
102   put(Permitted_operands, "f4", 0x00);
103   // inc
104   put(Permitted_operands, "40", 0x00);
105   put(Permitted_operands, "41", 0x00);
106   put(Permitted_operands, "42", 0x00);
107   put(Permitted_operands, "43", 0x00);
108   put(Permitted_operands, "44", 0x00);
109   put(Permitted_operands, "45", 0x00);
110   put(Permitted_operands, "46", 0x00);
111   put(Permitted_operands, "47", 0x00);
112   // dec
113   put(Permitted_operands, "48", 0x00);
114   put(Permitted_operands, "49", 0x00);
115   put(Permitted_operands, "4a", 0x00);
116   put(Permitted_operands, "4b", 0x00);
117   put(Permitted_operands, "4c", 0x00);
118   put(Permitted_operands, "4d", 0x00);
119   put(Permitted_operands, "4e", 0x00);
120   put(Permitted_operands, "4f", 0x00);
121   // push
122   put(Permitted_operands, "50", 0x00);
123   put(Permitted_operands, "51", 0x00);
124   put(Permitted_operands, "52", 0x00);
125   put(Permitted_operands, "53", 0x00);
126   put(Permitted_operands, "54", 0x00);
127   put(Permitted_operands, "55", 0x00);
128   put(Permitted_operands, "56", 0x00);
129   put(Permitted_operands, "57", 0x00);
130   // pop
131   put(Permitted_operands, "58", 0x00);
132   put(Permitted_operands, "59", 0x00);
133   put(Permitted_operands, "5a", 0x00);
134   put(Permitted_operands, "5b", 0x00);
135   put(Permitted_operands, "5c", 0x00);
136   put(Permitted_operands, "5d", 0x00);
137   put(Permitted_operands, "5e", 0x00);
138   put(Permitted_operands, "5f", 0x00);
139   // return
140   put(Permitted_operands, "c3", 0x00);
141 
142   //// Class B: just op and disp8
143   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
144   //  0     0     0      |0       1     0     0
145 
146   // jump
147   put(Permitted_operands, "eb", 0x04);
148   put(Permitted_operands, "74", 0x04);
149   put(Permitted_operands, "75", 0x04);
150   put(Permitted_operands, "7c", 0x04);
151   put(Permitted_operands, "7d", 0x04);
152   put(Permitted_operands, "7e", 0x04);
153   put(Permitted_operands, "7f", 0x04);
154 
155   //// Class D: just op and disp32
156   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
157   //  0     0     1      |0       0     0     0
158   put(Permitted_operands, "e8", 0x10);  // call
159   put(Permitted_operands, "e9", 0x10);  // jump
160 
161   //// Class E: just op and imm8
162   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
163   //  0     1     0      |0       0     0     0
164   put(Permitted_operands, "cd", 0x20);  // software interrupt
165 
166   //// Class F: just op and imm32
167   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
168   //  1     0     0      |0       0     0     0
169   put(Permitted_operands, "05", 0x40);  // add
170   put(Permitted_operands, "2d", 0x40);  // subtract
171   put(Permitted_operands, "25", 0x40);  // and
172   put(Permitted_operands, "0d", 0x40);  // or
173   put(Permitted_operands, "35", 0x40);  // xor
174   put(Permitted_operands, "3d", 0x40);  // compare
175   put(Permitted_operands, "68", 0x40);  // push
176   // copy
177   put(Permitted_operands, "b8", 0x40);
178   put(Permitted_operands, "b9", 0x40);
179   put(Permitted_operands, "ba", 0x40);
180   put(Permitted_operands, "bb", 0x40);
181   put(Permitted_operands, "bc", 0x40);
182   put(Permitted_operands, "bd", 0x40);
183   put(Permitted_operands, "be", 0x40);
184   put(Permitted_operands, "bf", 0x40);
185 
186   //// Class M: using ModR/M byte
187   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
188   //  0     0     0      |0       0     0     1
189 
190   // add
191   put(Permitted_operands, "01", 0x01);
192   put(Permitted_operands, "03", 0x01);
193   // subtract
194   put(Permitted_operands, "29", 0x01);
195   put(Permitted_operands, "2b", 0x01);
196   // and
197   put(Permitted_operands, "21", 0x01);
198   put(Permitted_operands, "23", 0x01);
199   // or
200   put(Permitted_operands, "09", 0x01);
201   put(Permitted_operands, "0b", 0x01);
202   // xor
203   put(Permitted_operands, "31", 0x01);
204   put(Permitted_operands, "33", 0x01);
205   // compare
206   put(Permitted_operands, "39", 0x01);
207   put(Permitted_operands, "3b", 0x01);
208   // copy
209   put(Permitted_operands, "88", 0x01);
210   put(Permitted_operands, "89", 0x01);
211   put(Permitted_operands, "8a", 0x01);
212   put(Permitted_operands, "8b", 0x01);
213   // swap
214   put(Permitted_operands, "87", 0x01);
215   // copy address (lea)
216   put(Permitted_operands, "8d", 0x01);
217   // pop
218   put(Permitted_operands, "8f", 0x01);
219 
220   //// Class N: op, ModR/M and subop (not r32)
221   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
222   //  0     0     0      |0       0     1     1
223   put(Permitted_operands, "d3", 0x03);  // shift
224   put(Permitted_operands, "f7", 0x03);  // test/not/mul/div
225   put(Permitted_operands, "ff", 0x03);  // jump/push/call
226 
227   //// Class O: op, ModR/M, subop (not r32) and imm8
228   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
229   //  0     1     0      |0       0     1     1
230   put(Permitted_operands, "c1", 0x23);  // combine
231 
232   //// Class P: op, ModR/M, subop (not r32) and imm32
233   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
234   //  1     0     0      |0       0     1     1
235   put(Permitted_operands, "81", 0x43);  // combine
236   put(Permitted_operands, "c7", 0x43);  // copy
237 
238   // End Init Permitted Operands
239 }
240 
241 :(code)
242 #define HAS(bitvector, bit)  ((bitvector) & (1 << (bit)))
243 #define SET(bitvector, bit)  ((bitvector) | (1 << (bit)))
244 #define CLEAR(bitvector, bit)  ((bitvector) & (~(1 << (bit))))
245 
246 void check_operands(const line& inst, const word& op) {
247   if (!is_hex_byte(op)) return;
248   uint8_t expected_bitvector = get(Permitted_operands, op.data);
249   if (HAS(expected_bitvector, MODRM)) {
250     check_operands_modrm(inst, op);
251     compare_bitvector_modrm(inst, expected_bitvector, op);
252   }
253   else {
254     compare_bitvector(inst, expected_bitvector, op);
255   }
256 }
257 
258 //: Many instructions can be checked just by comparing bitvectors.
259 
260 void compare_bitvector(const line& inst, uint8_t expected, const word& op) {
261   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
262   uint8_t bitvector = computed_expected_operand_bitvector(inst);
263   if (trace_contains_errors()) return;  // duplicate operand type
264   if (bitvector == expected) return;  // all good with this instruction
265   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
266 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
267     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
268     const string& optype = Operand_type_name.at(i);
269     if ((bitvector & 0x1) > (expected & 0x1))
270       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
271     else
272       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
273     // continue giving all errors for a single instruction
274   }
275   // ignore settings in any unused bits
276 }
277 
278 string maybe_name(const word& op) {
279   if (!is_hex_byte(op)) return "";
280   if (!contains_key(Name, op.data)) return "";
281   // strip stuff in parens from the name
282   const string& s = get(Name, op.data);
283   return " ("+s.substr(0, s.find(" ("))+')';
284 }
285 
286 uint32_t computed_expected_operand_bitvector(const line& inst) {
287   uint32_t bitvector = 0;
288   for (int i = /*skip op*/1;  i < SIZE(inst.words);  ++i) {
289     bitvector = bitvector | expected_bit_for_received_operand(inst.words.at(i));
290     if (trace_contains_errors()) return INVALID_OPERANDS;  // duplicate operand type
291   }
292   return bitvector;
293 }
294 
295 bool has_operands(const line& inst) {
296   return SIZE(inst.words) > first_operand(inst);
297 }
298 
299 int first_operand(const line& inst) {
300   if (inst.words.at(0).data == "0f") return 2;
301   if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
302     if (inst.words.at(1).data == "0f")
303       return 3;
304     else
305       return 2;
306   }
307   return 1;
308 }
309 
310 // Scan the metadata of 'w' and return the expected bit corresponding to any operand type.
311 // Also raise an error if metadata contains multiple operand types.
312 uint32_t expected_bit_for_received_operand(const word& w) {
313   uint32_t bv = 0;
314   bool found = false;
315   for (int i = 0;  i < SIZE(w.metadata);  ++i) {
316     string/*copy*/ curr = w.metadata.at(i);
317     if (curr == "mod" || curr == "rm32" || curr == "r32" || curr == "scale" || curr == "index" || curr == "base")
318       curr = "modrm";
319     else if (!contains_key(Operand_type, curr)) continue;  // ignore unrecognized metadata
320     if (found) {
321       raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
322       return INVALID_OPERANDS;
323     }
324     bv = (1 << get(Operand_type, curr));
325     found = true;
326   }
327   return bv;
328 }
329 
330 :(scenario conflicting_operand_type)
331 % Hide_errors = true;
332 == 0x1
333 cd/software-interrupt 80/imm8/imm32
334 +error: '80/imm8/imm32' has conflicting operand types; it should have only one
335 
336 //: Instructions computing effective addresses have more complex rules, so
337 //: we'll hard-code a common set of instruction-decoding rules.
338 
339 :(scenario check_missing_mod_operand)
340 % Hide_errors = true;
341 == 0x1
342 81 0/add/subop       3/rm32/ebx 1/imm32
343 +error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand
344 
345 :(code)
346 void check_operands_modrm(const line& inst, const word& op) {
347   if (all_hex_bytes(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
348   check_operand_metadata_present(inst, "mod", op);
349   check_operand_metadata_present(inst, "rm32", op);
350   // no check for r32; some instructions don't use it; just assume it's 0 if missing
351   if (op.data == "81" || op.data == "8f" || op.data == "ff") {  // keep sync'd with 'help subop'
352     check_operand_metadata_present(inst, "subop", op);
353     check_operand_metadata_absent(inst, "r32", op, "should be replaced by subop");
354   }
355   if (trace_contains_errors()) return;
356   if (metadata(inst, "rm32").data != "4") return;
357   // SIB byte checks
358   uint8_t mod = hex_byte(metadata(inst, "mod").data);
359   if (mod != /*direct*/3) {
360     check_operand_metadata_present(inst, "base", op);
361     check_operand_metadata_present(inst, "index", op);  // otherwise why go to SIB?
362   }
363   else {
364     check_operand_metadata_absent(inst, "base", op, "direct mode");
365     check_operand_metadata_absent(inst, "index", op, "direct mode");
366   }
367   // no check for scale; 0 (2**0 = 1) by default
368 }
369 
370 // same as compare_bitvector, with a couple of exceptions for modrm-based instructions
371 //   exception: modrm instructions can use a displacement on occasion
372 void compare_bitvector_modrm(const line& inst, uint8_t expected, const word& op) {
373   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
374   uint8_t bitvector = computed_expected_operand_bitvector(inst);
375   if (trace_contains_errors()) return;  // duplicate operand type
376   if (bitvector == expected) return;  // all good with this instruction
377   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
378 //?     cerr << "comparing for modrm " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
379     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
380     const string& optype = Operand_type_name.at(i);
381     if (i == DISP8) {
382       int32_t mod = parse_int(metadata(inst, "mod").data);
383       if (mod != 1)
384         raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
385       continue;  // exception 2
386     }
387     if (i == DISP32) {
388       int32_t mod = parse_int(metadata(inst, "mod").data);
389       int32_t rm32 = parse_int(metadata(inst, "rm32").data);
390       if (mod == 0 && rm32 == 5)
391         ;  // ok: special-case for loading address from disp32
392       else if (mod != 2)
393         raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
394       continue;  // exception 2
395     }
396     if ((bitvector & 0x1) > (expected & 0x1))
397       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
398     else
399       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
400     // continue giving all errors for a single instruction
401   }
402   // ignore settings in any unused bits
403 }
404 
405 void check_operand_metadata_present(const line& inst, const string& type, const word& op) {
406   if (!has_operand_metadata(inst, type))
407     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << type << " operand\n" << end();
408 }
409 
410 void check_operand_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
411   if (has_operand_metadata(inst, type))
412     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << type << " operand (" << msg << ")\n" << end();
413 }
414 
415 :(scenarios transform)
416 :(scenario modrm_with_displacement)
417 % Reg[EAX].u = 0x1;
418 == 0x1
419 # just avoid null pointer
420 8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8  # copy *(EAX+4) to EDX
421 $error: 0
422 :(scenarios run)
423 
424 :(scenario conflicting_operands_in_modrm_instruction)
425 % Hide_errors = true;
426 == 0x1
427 01/add 0/mod 3/mod
428 +error: '01/add 0/mod 3/mod' has conflicting mod operands
429 
430 :(scenario conflicting_operand_type_modrm)
431 % Hide_errors = true;
432 == 0x1
433 01/add 0/mod 3/rm32/r32
434 +error: '3/rm32/r32' has conflicting operand types; it should have only one
435 
436 :(scenario check_missing_rm32_operand)
437 % Hide_errors = true;
438 == 0x1
439 81 0/add/subop 0/mod            1/imm32
440 +error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand
441 
442 :(scenario check_missing_subop_operand)
443 % Hide_errors = true;
444 == 0x1
445 81             0/mod 3/rm32/ebx 1/imm32
446 +error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand
447 
448 :(scenario check_missing_base_operand)
449 % Hide_errors = true;
450 == 0x1
451 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32
452 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
453 
454 :(scenario check_missing_index_operand)
455 % Hide_errors = true;
456 == 0x1
457 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32
458 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand
459 
460 :(scenario check_missing_base_operand_2)
461 % Hide_errors = true;
462 == 0x1
463 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32
464 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
465 
466 :(scenario check_extra_displacement)
467 % Hide_errors = true;
468 == 0x1
469 89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8
470 +error: '89/copy 0/mod/indirect 0/rm32/EAX 1/r32/ECX 4/disp8' (copy r32 to rm32): unexpected disp8 operand
471 
472 :(scenario check_base_operand_not_needed_in_direct_mode)
473 == 0x1
474 81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32
475 $error: 0
476 
477 :(scenario extra_modrm)
478 % Hide_errors = true;
479 == 0x1
480 59/pop-to-ECX  3/mod/direct 1/rm32/ECX 4/r32/ESP
481 +error: '59/pop-to-ECX 3/mod/direct 1/rm32/ECX 4/r32/ESP' (pop top of stack to ECX): unexpected modrm operand
482 
483 //:: similarly handle multi-byte opcodes
484 
485 :(code)
486 void check_operands_0f(const line& inst) {
487   assert(inst.words.at(0).data == "0f");
488   if (SIZE(inst.words) == 1) {
489     raise << "opcode '0f' requires a second opcode\n" << end();
490     return;
491   }
492   word op = preprocess_op(inst.words.at(1));
493   if (!contains_key(Name_0f, op.data)) {
494     raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
495     return;
496   }
497   check_operands_0f(inst, op);
498 }
499 
500 void check_operands_f3(const line& /*unused*/) {
501   raise << "no supported opcodes starting with f3\n" << end();
502 }
503 
504 :(scenario check_missing_disp32_operand)
505 % Hide_errors = true;
506 == 0x1
507 # instruction                     effective address                                                   operand     displacement    immediate
508 # op          subop               mod             rm32          base        index         scale       r32
509 # 1-3 bytes   3 bits              2 bits          3 bits        3 bits      3 bits        2 bits      2 bits      0/1/2/4 bytes   0/1/2/4 bytes
510   0f 84                                                                                                                                             # jmp if ZF to ??
511 +error: '0f 84' (jump disp32 bytes away if equal, if ZF is set): missing disp32 operand
512 
513 :(before "End Globals")
514 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands_0f;
515 :(before "End Init Permitted Operands")
516 //// Class D: just op and disp32
517 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
518 //  0     0     1      |0       0     0     0
519 put_new(Permitted_operands_0f, "84", 0x10);
520 put_new(Permitted_operands_0f, "85", 0x10);
521 put_new(Permitted_operands_0f, "8c", 0x10);
522 put_new(Permitted_operands_0f, "8d", 0x10);
523 put_new(Permitted_operands_0f, "8e", 0x10);
524 put_new(Permitted_operands_0f, "8f", 0x10);
525 
526 //// Class M: using ModR/M byte
527 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
528 //  0     0     0      |0       0     0     1
529 put_new(Permitted_operands_0f, "af", 0x01);
530 
531 :(code)
532 void check_operands_0f(const line& inst, const word& op) {
533   uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
534   if (HAS(expected_bitvector, MODRM))
535     check_operands_modrm(inst, op);
536   compare_bitvector_0f(inst, CLEAR(expected_bitvector, MODRM), op);
537 }
538 
539 void compare_bitvector_0f(const line& inst, uint8_t expected, const word& op) {
540   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
541   uint8_t bitvector = computed_expected_operand_bitvector(inst);
542   if (trace_contains_errors()) return;  // duplicate operand type
543   if (bitvector == expected) return;  // all good with this instruction
544   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
545 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
546     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
547     const string& optype = Operand_type_name.at(i);
548     if ((bitvector & 0x1) > (expected & 0x1))
549       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": unexpected " << optype << " operand\n" << end();
550     else
551       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": missing " << optype << " operand\n" << end();
552     // continue giving all errors for a single instruction
553   }
554   // ignore settings in any unused bits
555 }
556 
557 string maybe_name_0f(const word& op) {
558   if (!is_hex_byte(op)) return "";
559   if (!contains_key(Name_0f, op.data)) return "";
560   // strip stuff in parens from the name
561   const string& s = get(Name_0f, op.data);
562   return " ("+s.substr(0, s.find(" ("))+')';
563 }
564 
565 string tolower(const char* s) {
566   ostringstream out;
567   for (/*nada*/;  *s;  ++s)
568     out << static_cast<char>(tolower(*s));
569   return out.str();
570 }
571 
572 #undef HAS
573 #undef SET
574 #undef CLEAR
575 
576 :(before "End Includes")
577 #include<cctype>