1 //: Since we're tagging operands with their types, let's start checking these
  2 //: operand types for each instruction.
  3 
  4 :(scenario check_missing_imm8_operand)
  5 % Hide_errors = true;
  6 == 0x1
  7 # instruction                     effective address                                                   operand     displacement    immediate
  8 # op          subop               mod             rm32          base        index         scale       r32
  9 # 1-3 bytes   3 bits              2 bits          3 bits        3 bits      3 bits        2 bits      2 bits      0/1/2/4 bytes   0/1/2/4 bytes
 10   cd                                                                                                                                                # int ??
 11 +error: 'cd' (software interrupt): missing imm8 operand
 12 
 13 :(before "Pack Operands(segment code)")
 14 check_operands(code);
 15 if (trace_contains_errors()) return;
 16 
 17 :(code)
 18 void check_operands(const segment& code) {
 19   trace(99, "transform") << "-- check operands" << end();
 20   for (int i = 0;  i < SIZE(code.lines);  ++i) {
 21     check_operands(code.lines.at(i));
 22     if (trace_contains_errors()) return;  // stop at the first mal-formed instruction
 23   }
 24 }
 25 
 26 void check_operands(const line& inst) {
 27   word op = preprocess_op(inst.words.at(0));
 28   if (op.data == "0f") {
 29     check_operands_0f(inst);
 30     return;
 31   }
 32   if (op.data == "f3") {
 33     check_operands_f3(inst);
 34     return;
 35   }
 36   check_operands(inst, op);
 37 }
 38 
 39 word preprocess_op(word/*copy*/ op) {
 40   op.data = tolower(op.data.c_str());
 41   // opcodes can't be negative
 42   if (starts_with(op.data, "0x"))
 43     op.data = op.data.substr(2);
 44   if (SIZE(op.data) == 1)
 45     op.data = string("0")+op.data;
 46   return op;
 47 }
 48 
 49 void test_preprocess_op() {
 50   word w1;  w1.data = "0xf";
 51   word w2;  w2.data = "0f";
 52   CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
 53 }
 54 
 55 //: To check the operands for an opcode, we'll track the permitted operands
 56 //: for each supported opcode in a bitvector. That way we can often compute the
 57 //: bitvector for each instruction's operands and compare it with the expected.
 58 
 59 :(before "End Types")
 60 enum operand_type {
 61   // start from the least significant bit
 62   MODRM,  // more complex, may also involve disp8 or disp32
 63   SUBOP,
 64   DISP8,
 65   DISP16,
 66   DISP32,
 67   IMM8,
 68   IMM32,
 69   NUM_OPERAND_TYPES
 70 };
 71 :(before "End Globals")
 72 vector<string> Operand_type_name;
 73 map<string, operand_type> Operand_type;
 74 :(before "End One-time Setup")
 75 init_op_types();
 76 :(code)
 77 void init_op_types() {
 78   assert(NUM_OPERAND_TYPES <= /*bits in a uint8_t*/8);
 79   Operand_type_name.resize(NUM_OPERAND_TYPES);
 80   #define DEF(type) Operand_type_name.at(type) = tolower(#type), put(Operand_type, tolower(#type), type);
 81   DEF(MODRM);
 82   DEF(SUBOP);
 83   DEF(DISP8);
 84   DEF(DISP16);
 85   DEF(DISP32);
 86   DEF(IMM8);
 87   DEF(IMM32);
 88   #undef DEF
 89 }
 90 
 91 :(before "End Globals")
 92 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands;
 93 const uint8_t INVALID_OPERANDS = 0xff;  // no instruction uses all the operand types
 94 :(before "End One-time Setup")
 95 init_permitted_operands();
 96 :(code)
 97 void init_permitted_operands() {
 98   //// Class A: just op, no operands
 99   // halt
100   put(Permitted_operands, "f4", 0x00);
101   // push
102   put(Permitted_operands, "50", 0x00);
103   put(Permitted_operands, "51", 0x00);
104   put(Permitted_operands, "52", 0x00);
105   put(Permitted_operands, "53", 0x00);
106   put(Permitted_operands, "54", 0x00);
107   put(Permitted_operands, "55", 0x00);
108   put(Permitted_operands, "56", 0x00);
109   put(Permitted_operands, "57", 0x00);
110   // pop
111   put(Permitted_operands, "58", 0x00);
112   put(Permitted_operands, "59", 0x00);
113   put(Permitted_operands, "5a", 0x00);
114   put(Permitted_operands, "5b", 0x00);
115   put(Permitted_operands, "5c", 0x00);
116   put(Permitted_operands, "5d", 0x00);
117   put(Permitted_operands, "5e", 0x00);
118   put(Permitted_operands, "5f", 0x00);
119   // return
120   put(Permitted_operands, "c3", 0x00);
121 
122   //// Class B: just op and disp8
123   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
124   //  0     0     0      |0       1     0     0
125 
126   // jump
127   put(Permitted_operands, "eb", 0x04);
128   put(Permitted_operands, "74", 0x04);
129   put(Permitted_operands, "75", 0x04);
130   put(Permitted_operands, "7c", 0x04);
131   put(Permitted_operands, "7d", 0x04);
132   put(Permitted_operands, "7e", 0x04);
133   put(Permitted_operands, "7f", 0x04);
134 
135   //// Class C: just op and disp16
136   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
137   //  0     0     0      |1       0     0     0
138   put(Permitted_operands, "e9", 0x08);  // jump
139 
140   //// Class D: just op and disp32
141   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
142   //  0     0     1      |0       0     0     0
143   put(Permitted_operands, "e8", 0x10);  // call
144 
145   //// Class E: just op and imm8
146   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
147   //  0     1     0      |0       0     0     0
148   put(Permitted_operands, "cd", 0x20);  // software interrupt
149 
150   //// Class F: just op and imm32
151   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
152   //  1     0     0      |0       0     0     0
153   put(Permitted_operands, "05", 0x40);  // add
154   put(Permitted_operands, "2d", 0x40);  // subtract
155   put(Permitted_operands, "25", 0x40);  // and
156   put(Permitted_operands, "0d", 0x40);  // or
157   put(Permitted_operands, "35", 0x40);  // xor
158   put(Permitted_operands, "3d", 0x40);  // compare
159   put(Permitted_operands, "68", 0x40);  // push
160   // copy
161   put(Permitted_operands, "b8", 0x40);
162   put(Permitted_operands, "b9", 0x40);
163   put(Permitted_operands, "ba", 0x40);
164   put(Permitted_operands, "bb", 0x40);
165   put(Permitted_operands, "bc", 0x40);
166   put(Permitted_operands, "bd", 0x40);
167   put(Permitted_operands, "be", 0x40);
168   put(Permitted_operands, "bf", 0x40);
169 
170   //// Class M: using ModR/M byte
171   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
172   //  0     0     0      |0       0     0     1
173 
174   // add
175   put(Permitted_operands, "01", 0x01);
176   put(Permitted_operands, "03", 0x01);
177   // subtract
178   put(Permitted_operands, "29", 0x01);
179   put(Permitted_operands, "2b", 0x01);
180   // and
181   put(Permitted_operands, "21", 0x01);
182   put(Permitted_operands, "23", 0x01);
183   // or
184   put(Permitted_operands, "09", 0x01);
185   put(Permitted_operands, "0b", 0x01);
186   // xor
187   put(Permitted_operands, "31", 0x01);
188   put(Permitted_operands, "33", 0x01);
189   // compare
190   put(Permitted_operands, "39", 0x01);
191   put(Permitted_operands, "3b", 0x01);
192   // copy
193   put(Permitted_operands, "88", 0x01);
194   put(Permitted_operands, "89", 0x01);
195   put(Permitted_operands, "8a", 0x01);
196   put(Permitted_operands, "8b", 0x01);
197   // swap
198   put(Permitted_operands, "87", 0x01);
199   // pop
200   put(Permitted_operands, "8f", 0x01);
201 
202   //// Class O: op, ModR/M and subop (not r32)
203   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
204   //  0     0     0      |0       0     1     1
205   put(Permitted_operands, "f7", 0x03);  // test/not/mul/div
206   put(Permitted_operands, "ff", 0x03);  // jump/push/call
207 
208   //// Class N: op, ModR/M and imm32
209   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
210   //  1     0     0      |0       0     0     1
211   put(Permitted_operands, "c7", 0x41);  // copy
212 
213   //// Class P: op, ModR/M, subop (not r32) and imm32
214   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
215   //  1     0     0      |0       0     1     1
216   put(Permitted_operands, "81", 0x43);  // combine
217 
218   // End Init Permitted Operands
219 }
220 
221 :(code)
222 #define HAS(bitvector, bit)  ((bitvector) & (1 << (bit)))
223 #define SET(bitvector, bit)  ((bitvector) | (1 << (bit)))
224 #define CLEAR(bitvector, bit)  ((bitvector) & (~(1 << (bit))))
225 
226 void check_operands(const line& inst, const word& op) {
227   if (!is_hex_byte(op)) return;
228   uint8_t expected_bitvector = get(Permitted_operands, op.data);
229   if (HAS(expected_bitvector, MODRM)) {
230     check_operands_modrm(inst, op);
231     compare_bitvector_modrm(inst, expected_bitvector, op);
232   }
233   else {
234     compare_bitvector(inst, expected_bitvector, op);
235   }
236 }
237 
238 //: Many instructions can be checked just by comparing bitvectors.
239 
240 void compare_bitvector(const line& inst, uint8_t expected, const word& op) {
241   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
242   uint8_t bitvector = compute_operand_bitvector(inst);
243   if (trace_contains_errors()) return;  // duplicate operand type
244   if (bitvector == expected) return;  // all good with this instruction
245   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
246 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
247     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
248     const string& optype = Operand_type_name.at(i);
249     if ((bitvector & 0x1) > (expected & 0x1))
250       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
251     else
252       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
253     // continue giving all errors for a single instruction
254   }
255   // ignore settings in any unused bits
256 }
257 
258 string maybe_name(const word& op) {
259   if (!is_hex_byte(op)) return "";
260   if (!contains_key(name, op.data)) return "";
261   return " ("+get(name, op.data)+')';
262 }
263 
264 uint32_t compute_operand_bitvector(const line& inst) {
265   uint32_t bitvector = 0;
266   for (int i = /*skip op*/1;  i < SIZE(inst.words);  ++i) {
267     bitvector = bitvector | bitvector_for_operand(inst.words.at(i));
268     if (trace_contains_errors()) return INVALID_OPERANDS;  // duplicate operand type
269   }
270   return bitvector;
271 }
272 
273 bool has_operands(const line& inst) {
274   return SIZE(inst.words) > first_operand(inst);
275 }
276 
277 int first_operand(const line& inst) {
278   if (inst.words.at(0).data == "0f") return 2;
279   if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
280     if (inst.words.at(1).data == "0f")
281       return 3;
282     else
283       return 2;
284   }
285   return 1;
286 }
287 
288 // Scan the metadata of 'w' and return the bit corresponding to any operand type.
289 // Also raise an error if metadata contains multiple operand types.
290 uint32_t bitvector_for_operand(const word& w) {
291   uint32_t bv = 0;
292   bool found = false;
293   for (int i = 0;  i < SIZE(w.metadata);  ++i) {
294     const string& curr = w.metadata.at(i);
295     if (!contains_key(Operand_type, curr)) continue;  // ignore unrecognized metadata
296     if (found) {
297       raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
298       return INVALID_OPERANDS;
299     }
300     bv = (1 << get(Operand_type, curr));
301     found = true;
302   }
303   return bv;
304 }
305 
306 :(scenario conflicting_operand_type)
307 % Hide_errors = true;
308 == 0x1
309 cd/software-interrupt 80/imm8/imm32
310 +error: '80/imm8/imm32' has conflicting operand types; it should have only one
311 
312 //: Instructions computing effective addresses have more complex rules, so
313 //: we'll hard-code a common set of instruction-decoding rules.
314 
315 :(scenario check_missing_mod_operand)
316 % Hide_errors = true;
317 == 0x1
318 81 0/add/subop       3/rm32/ebx 1/imm32
319 +error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand
320 
321 :(code)
322 void check_operands_modrm(const line& inst, const word& op) {
323   if (all_hex_bytes(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
324   check_metadata_present(inst, "mod", op);
325   check_metadata_present(inst, "rm32", op);
326   // no check for r32; some instructions don't use it; just assume it's 0 if missing
327   if (op.data == "81" || op.data == "8f" || op.data == "ff") {  // keep sync'd with 'help subop'
328     check_metadata_present(inst, "subop", op);
329     check_metadata_absent(inst, "r32", op, "should be replaced by subop");
330   }
331   if (trace_contains_errors()) return;
332   if (metadata(inst, "rm32").data != "4") return;
333   // SIB byte checks
334   uint8_t mod = hex_byte(metadata(inst, "mod").data);
335   if (mod != /*direct*/3) {
336     check_metadata_present(inst, "base", op);
337     check_metadata_present(inst, "index", op);  // otherwise why go to SIB?
338   }
339   else {
340     check_metadata_absent(inst, "base", op, "direct mode");
341     check_metadata_absent(inst, "index", op, "direct mode");
342   }
343   // no check for scale; 0 (2**0 = 1) by default
344 }
345 
346 // same as compare_bitvector, with a couple of exceptions for modrm-based instructions
347 //   exception 1: ignore modrm bit since we already checked it above
348 //   exception 2: modrm instructions can use a displacement on occasion
349 void compare_bitvector_modrm(const line& inst, uint8_t expected, const word& op) {
350   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
351   uint8_t bitvector = compute_operand_bitvector(inst);
352   if (trace_contains_errors()) return;  // duplicate operand type
353   expected = CLEAR(expected, MODRM);  // exception 1
354   if (bitvector == expected) return;  // all good with this instruction
355   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
356 //?     cerr << "comparing for modrm " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
357     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
358     if (i == DISP8 || i == DISP32) continue;  // exception 2
359     const string& optype = Operand_type_name.at(i);
360     if ((bitvector & 0x1) > (expected & 0x1))
361       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
362     else
363       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
364     // continue giving all errors for a single instruction
365   }
366   // ignore settings in any unused bits
367 }
368 
369 void check_metadata_present(const line& inst, const string& type, const word& op) {
370   if (!has_metadata(inst, type))
371     raise << "'" << to_string(inst) << "' (" << get(name, op.data) << "): missing " << type << " operand\n" << end();
372 }
373 
374 void check_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
375   if (has_metadata(inst, type))
376     raise << "'" << to_string(inst) << "' (" << get(name, op.data) << "): unexpected " << type << " operand (" << msg << ")\n" << end();
377 }
378 
379 :(scenarios transform)
380 :(scenario modrm_with_displacement)
381 % Reg[EAX].u = 0x1;
382 == 0x1
383 # just avoid null pointer
384 8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8  # copy *(EAX+4) to EDX
385 $error: 0
386 :(scenarios run)
387 
388 :(scenario conflicting_operands_in_modrm_instruction)
389 % Hide_errors = true;
390 == 0x1
391 01/add 0/mod 3/mod
392 +error: '01/add 0/mod 3/mod' has conflicting mod operands
393 
394 :(scenario conflicting_operand_type_modrm)
395 % Hide_errors = true;
396 == 0x1
397 01/add 0/mod 3/rm32/r32
398 +error: '3/rm32/r32' has conflicting operand types; it should have only one
399 
400 :(scenario check_missing_rm32_operand)
401 % Hide_errors = true;
402 == 0x1
403 81 0/add/subop 0/mod            1/imm32
404 +error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand
405 
406 :(scenario check_missing_subop_operand)
407 % Hide_errors = true;
408 == 0x1
409 81             0/mod 3/rm32/ebx 1/imm32
410 +error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand
411 
412 :(scenario check_missing_base_operand)
413 % Hide_errors = true;
414 == 0x1
415 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32
416 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
417 
418 :(scenario check_missing_index_operand)
419 % Hide_errors = true;
420 == 0x1
421 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32
422 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand
423 
424 :(scenario check_missing_base_operand_2)
425 % Hide_errors = true;
426 == 0x1
427 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32
428 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
429 
430 :(scenario check_base_operand_not_needed_in_direct_mode)
431 == 0x1
432 81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32
433 $error: 0
434 
435 //:: similarly handle multi-byte opcodes
436 
437 :(code)
438 void check_operands_0f(const line& inst) {
439   assert(inst.words.at(0).data == "0f");
440   if (SIZE(inst.words) == 1) {
441     raise << "opcode '0f' requires a second opcode\n" << end();
442     return;
443   }
444   word op = preprocess_op(inst.words.at(1));
445   if (!contains_key(name_0f, op.data)) {
446     raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
447     return;
448   }
449   check_operands_0f(inst, op);
450 }
451 
452 void check_operands_f3(const line& /*unused*/) {
453   raise << "no supported opcodes starting with f3\n" << end();
454 }
455 
456 :(scenario check_missing_disp16_operand)
457 % Hide_errors = true;
458 == 0x1
459 # instruction                     effective address                                                   operand     displacement    immediate
460 # op          subop               mod             rm32          base        index         scale       r32
461 # 1-3 bytes   3 bits              2 bits          3 bits        3 bits      3 bits        2 bits      2 bits      0/1/2/4 bytes   0/1/2/4 bytes
462   0f 84                                                                                                                                             # jmp if ZF to ??
463 +error: '0f 84' (jump disp16 bytes away if ZF is set): missing disp16 operand
464 
465 :(before "End Globals")
466 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands_0f;
467 :(before "End Init Permitted Operands")
468 //// Class C: just op and disp16
469 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
470 //  0     0     0      |1       0     0     0
471 put(Permitted_operands_0f, "84", 0x08);
472 put(Permitted_operands_0f, "85", 0x08);
473 put(Permitted_operands_0f, "8c", 0x08);
474 put(Permitted_operands_0f, "8d", 0x08);
475 put(Permitted_operands_0f, "8e", 0x08);
476 put(Permitted_operands_0f, "8f", 0x08);
477 
478 //// Class M: using ModR/M byte
479 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
480 //  0     0     0      |0       0     0     1
481 put(Permitted_operands_0f, "af", 0x01);
482 
483 :(code)
484 void check_operands_0f(const line& inst, const word& op) {
485   uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
486   if (HAS(expected_bitvector, MODRM))
487     check_operands_modrm(inst, op);
488   compare_bitvector_0f(inst, CLEAR(expected_bitvector, MODRM), op);
489 }
490 
491 void compare_bitvector_0f(const line& inst, uint8_t expected, const word& op) {
492   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
493   uint8_t bitvector = compute_operand_bitvector(inst);
494   if (trace_contains_errors()) return;  // duplicate operand type
495   if (bitvector == expected) return;  // all good with this instruction
496   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
497 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
498     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
499     const string& optype = Operand_type_name.at(i);
500     if ((bitvector & 0x1) > (expected & 0x1))
501       raise << "'" << to_string(inst) << "' (" << get(name_0f, op.data) << "): unexpected " << optype << " operand\n" << end();
502     else
503       raise << "'" << to_string(inst) << "' (" << get(name_0f, op.data) << "): missing " << optype << " operand\n" << end();
504     // continue giving all errors for a single instruction
505   }
506   // ignore settings in any unused bits
507 }
508 
509 string tolower(const char* s) {
510   ostringstream out;
511   for (/*nada*/;  *s;  ++s)
512     out << static_cast<char>(tolower(*s));
513   return out.str();
514 }
515 
516 #undef HAS
517 #undef SET
518 #undef CLEAR
519 
520 :(before "End Includes")
521 #include<cctype>