1
2
3
4 :(scenario check_missing_imm8_operand)
5 % Hide_errors = true;
6 == 0x1
7
8
9
10 cd
11 +error: 'cd' (software interrupt): missing imm8 operand
12
13 :(before "Pack Operands(segment code)")
14 check_operands(code);
15 if (trace_contains_errors()) return;
16
17 :(code)
18 void check_operands(const segment& code) {
19 trace(99, "transform") << "-- check operands" << end();
20 for (int i = 0; i < SIZE(code.lines); ++i) {
21 check_operands(code.lines.at(i));
22 if (trace_contains_errors()) return;
23 }
24 }
25
26 void check_operands(const line& inst) {
27 word op = preprocess_op(inst.words.at(0));
28 if (op.data == "0f") {
29 check_operands_0f(inst);
30 return;
31 }
32 if (op.data == "f3") {
33 check_operands_f3(inst);
34 return;
35 }
36 check_operands(inst, op);
37 }
38
39 word preprocess_op(word op) {
40 op.data = tolower(op.data.c_str());
41
42 if (starts_with(op.data, "0x"))
43 op.data = op.data.substr(2);
44 if (SIZE(op.data) == 1)
45 op.data = string("0")+op.data;
46 return op;
47 }
48
49 void test_preprocess_op() {
50 word w1; w1.data = "0xf";
51 word w2; w2.data = "0f";
52 CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
53 }
54
55
56
57
58
59 :(before "End Types")
60 enum operand_type {
61
62 MODRM,
63 SUBOP,
64 DISP8,
65 DISP16,
66 DISP32,
67 IMM8,
68 IMM32,
69 NUM_OPERAND_TYPES
70 };
71 :(before "End Globals")
72 vector<string> Operand_type_name;
73 map<string, operand_type> Operand_type;
74 :(before "End One-time Setup")
75 init_op_types();
76 :(code)
77 void init_op_types() {
78 assert(NUM_OPERAND_TYPES <= 8);
79 Operand_type_name.resize(NUM_OPERAND_TYPES);
80
81 DEF(MODRM);
82 DEF(SUBOP);
83 DEF(DISP8);
84 DEF(DISP16);
85 DEF(DISP32);
86 DEF(IMM8);
87 DEF(IMM32);
88
89 }
90
91 :(before "End Globals")
92 map<string, uint8_t> Permitted_operands;
93 const uint8_t INVALID_OPERANDS = 0xff;
94 :(before "End One-time Setup")
95 init_permitted_operands();
96 :(code)
97 void init_permitted_operands() {
98
99
100 put(Permitted_operands, "f4", 0x00);
101
102 put(Permitted_operands, "40", 0x00);
103 put(Permitted_operands, "41", 0x00);
104 put(Permitted_operands, "42", 0x00);
105 put(Permitted_operands, "43", 0x00);
106 put(Permitted_operands, "44", 0x00);
107 put(Permitted_operands, "45", 0x00);
108 put(Permitted_operands, "46", 0x00);
109 put(Permitted_operands, "47", 0x00);
110
111 put(Permitted_operands, "48", 0x00);
112 put(Permitted_operands, "49", 0x00);
113 put(Permitted_operands, "4a", 0x00);
114 put(Permitted_operands, "4b", 0x00);
115 put(Permitted_operands, "4c", 0x00);
116 put(Permitted_operands, "4d", 0x00);
117 put(Permitted_operands, "4e", 0x00);
118 put(Permitted_operands, "4f", 0x00);
119
120 put(Permitted_operands, "50", 0x00);
121 put(Permitted_operands, "51", 0x00);
122 put(Permitted_operands, "52", 0x00);
123 put(Permitted_operands, "53", 0x00);
124 put(Permitted_operands, "54", 0x00);
125 put(Permitted_operands, "55", 0x00);
126 put(Permitted_operands, "56", 0x00);
127 put(Permitted_operands, "57", 0x00);
128
129 put(Permitted_operands, "58", 0x00);
130 put(Permitted_operands, "59", 0x00);
131 put(Permitted_operands, "5a", 0x00);
132 put(Permitted_operands, "5b", 0x00);
133 put(Permitted_operands, "5c", 0x00);
134 put(Permitted_operands, "5d", 0x00);
135 put(Permitted_operands, "5e", 0x00);
136 put(Permitted_operands, "5f", 0x00);
137
138 put(Permitted_operands, "c3", 0x00);
139
140
141
142
143
144
145 put(Permitted_operands, "eb", 0x04);
146 put(Permitted_operands, "74", 0x04);
147 put(Permitted_operands, "75", 0x04);
148 put(Permitted_operands, "7c", 0x04);
149 put(Permitted_operands, "7d", 0x04);
150 put(Permitted_operands, "7e", 0x04);
151 put(Permitted_operands, "7f", 0x04);
152
153
154
155
156 put(Permitted_operands, "e9", 0x08);
157
158
159
160
161 put(Permitted_operands, "e8", 0x10);
162
163
164
165
166 put(Permitted_operands, "cd", 0x20);
167
168
169
170
171 put(Permitted_operands, "05", 0x40);
172 put(Permitted_operands, "2d", 0x40);
173 put(Permitted_operands, "25", 0x40);
174 put(Permitted_operands, "0d", 0x40);
175 put(Permitted_operands, "35", 0x40);
176 put(Permitted_operands, "3d", 0x40);
177 put(Permitted_operands, "68", 0x40);
178
179 put(Permitted_operands, "b8", 0x40);
180 put(Permitted_operands, "b9", 0x40);
181 put(Permitted_operands, "ba", 0x40);
182 put(Permitted_operands, "bb", 0x40);
183 put(Permitted_operands, "bc", 0x40);
184 put(Permitted_operands, "bd", 0x40);
185 put(Permitted_operands, "be", 0x40);
186 put(Permitted_operands, "bf", 0x40);
187
188
189
190
191
192
193 put(Permitted_operands, "01", 0x01);
194 put(Permitted_operands, "03", 0x01);
195
196 put(Permitted_operands, "29", 0x01);
197 put(Permitted_operands, "2b", 0x01);
198
199 put(Permitted_operands, "21", 0x01);
200 put(Permitted_operands, "23", 0x01);
201
202 put(Permitted_operands, "09", 0x01);
203 put(Permitted_operands, "0b", 0x01);
204
205 put(Permitted_operands, "31", 0x01);
206 put(Permitted_operands, "33", 0x01);
207
208 put(Permitted_operands, "39", 0x01);
209 put(Permitted_operands, "3b", 0x01);
210
211 put(Permitted_operands, "88", 0x01);
212 put(Permitted_operands, "89", 0x01);
213 put(Permitted_operands, "8a", 0x01);
214 put(Permitted_operands, "8b", 0x01);
215
216 put(Permitted_operands, "87", 0x01);
217
218 put(Permitted_operands, "8f", 0x01);
219
220
221
222
223 put(Permitted_operands, "f7", 0x03);
224 put(Permitted_operands, "ff", 0x03);
225
226
227
228
229 put(Permitted_operands, "c7", 0x41);
230
231
232
233
234 put(Permitted_operands, "81", 0x43);
235
236
237 }
238
239 :(code)
240
241
242
243
244 void check_operands(const line& inst, const word& op) {
245 if (!is_hex_byte(op)) return;
246 uint8_t expected_bitvector = get(Permitted_operands, op.data);
247 if (HAS(expected_bitvector, MODRM)) {
248 check_operands_modrm(inst, op);
249 compare_bitvector_modrm(inst, expected_bitvector, op);
250 }
251 else {
252 compare_bitvector(inst, expected_bitvector, op);
253 }
254 }
255
256
257
258 void compare_bitvector(const line& inst, uint8_t expected, const word& op) {
259 if (all_hex_bytes(inst) && has_operands(inst)) return;
260 uint8_t bitvector = compute_operand_bitvector(inst);
261 if (trace_contains_errors()) return;
262 if (bitvector == expected) return;
263 for (int i = 0; i < NUM_OPERAND_TYPES; ++i, bitvector >>= 1, expected >>= 1) {
264
265 if ((bitvector & 0x1) == (expected & 0x1)) continue;
266 const string& optype = Operand_type_name.at(i);
267 if ((bitvector & 0x1) > (expected & 0x1))
268 raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
269 else
270 raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
271
272 }
273
274 }
275
276 string maybe_name(const word& op) {
277 if (!is_hex_byte(op)) return "";
278 if (!contains_key(name, op.data)) return "";
279 return " ("+get(name, op.data)+')';
280 }
281
282 uint32_t compute_operand_bitvector(const line& inst) {
283 uint32_t bitvector = 0;
284 for (int i = 1; i < SIZE(inst.words); ++i) {
285 bitvector = bitvector | bitvector_for_operand(inst.words.at(i));
286 if (trace_contains_errors()) return INVALID_OPERANDS;
287 }
288 return bitvector;
289 }
290
291 bool has_operands(const line& inst) {
292 return SIZE(inst.words) > first_operand(inst);
293 }
294
295 int first_operand(const line& inst) {
296 if (inst.words.at(0).data == "0f") return 2;
297 if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
298 if (inst.words.at(1).data == "0f")
299 return 3;
300 else
301 return 2;
302 }
303 return 1;
304 }
305
306
307
308 uint32_t bitvector_for_operand(const word& w) {
309 uint32_t bv = 0;
310 bool found = false;
311 for (int i = 0; i < SIZE(w.metadata); ++i) {
312 const string& curr = w.metadata.at(i);
313 if (!contains_key(Operand_type, curr)) continue;
314 if (found) {
315 raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
316 return INVALID_OPERANDS;
317 }
318 bv = (1 << get(Operand_type, curr));
319 found = true;
320 }
321 return bv;
322 }
323
324 :(scenario conflicting_operand_type)
325 % Hide_errors = true;
326 == 0x1
327 cd/software-interrupt 80/imm8/imm32
328 +error: '80/imm8/imm32' has conflicting operand types; it should have only one
329
330
331
332
333 :(scenario check_missing_mod_operand)
334 % Hide_errors = true;
335 == 0x1
336 81 0/add/subop 3/rm32/ebx 1/imm32
337 +error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand
338
339 :(code)
340 void check_operands_modrm(const line& inst, const word& op) {
341 if (all_hex_bytes(inst)) return;
342 check_operand_metadata_present(inst, "mod", op);
343 check_operand_metadata_present(inst, "rm32", op);
344
345 if (op.data == "81" || op.data == "8f" || op.data == "ff") {
346 check_operand_metadata_present(inst, "subop", op);
347 check_operand_metadata_absent(inst, "r32", op, "should be replaced by subop");
348 }
349 if (trace_contains_errors()) return;
350 if (metadata(inst, "rm32").data != "4") return;
351
352 uint8_t mod = hex_byte(metadata(inst, "mod").data);
353 if (mod != 3) {
354 check_operand_metadata_present(inst, "base", op);
355 check_operand_metadata_present(inst, "index", op);
356 }
357 else {
358 check_operand_metadata_absent(inst, "base", op, "direct mode");
359 check_operand_metadata_absent(inst, "index", op, "direct mode");
360 }
361
362 }
363
364
365
366
367 void compare_bitvector_modrm(const line& inst, uint8_t expected, const word& op) {
368 if (all_hex_bytes(inst) && has_operands(inst)) return;
369 uint8_t bitvector = compute_operand_bitvector(inst);
370 if (trace_contains_errors()) return;
371 expected = CLEAR(expected, MODRM);
372 if (bitvector == expected) return;
373 for (int i = 0; i < NUM_OPERAND_TYPES; ++i, bitvector >>= 1, expected >>= 1) {
374
375 if ((bitvector & 0x1) == (expected & 0x1)) continue;
376 if (i == DISP8 || i == DISP32) continue;
377 const string& optype = Operand_type_name.at(i);
378 if ((bitvector & 0x1) > (expected & 0x1))
379 raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
380 else
381 raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
382
383 }
384
385 }
386
387 void check_operand_metadata_present(const line& inst, const string& type, const word& op) {
388 if (!has_operand_metadata(inst, type))
389 raise << "'" << to_string(inst) << "' (" << get(name, op.data) << "): missing " << type << " operand\n" << end();
390 }
391
392 void check_operand_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
393 if (has_operand_metadata(inst, type))
394 raise << "'" << to_string(inst) << "' (" << get(name, op.data) << "): unexpected " << type << " operand (" << msg << ")\n" << end();
395 }
396
397 :(scenarios transform)
398 :(scenario modrm_with_displacement)
399 % Reg[EAX].u = 0x1;
400 == 0x1
401
402 8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8
403 $error: 0
404 :(scenarios run)
405
406 :(scenario conflicting_operands_in_modrm_instruction)
407 % Hide_errors = true;
408 == 0x1
409 01/add 0/mod 3/mod
410 +error: '01/add 0/mod 3/mod' has conflicting mod operands
411
412 :(scenario conflicting_operand_type_modrm)
413 % Hide_errors = true;
414 == 0x1
415 01/add 0/mod 3/rm32/r32
416 +error: '3/rm32/r32' has conflicting operand types; it should have only one
417
418 :(scenario check_missing_rm32_operand)
419 % Hide_errors = true;
420 == 0x1
421 81 0/add/subop 0/mod 1/imm32
422 +error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand
423
424 :(scenario check_missing_subop_operand)
425 % Hide_errors = true;
426 == 0x1
427 81 0/mod 3/rm32/ebx 1/imm32
428 +error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand
429
430 :(scenario check_missing_base_operand)
431 % Hide_errors = true;
432 == 0x1
433 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32
434 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
435
436 :(scenario check_missing_index_operand)
437 % Hide_errors = true;
438 == 0x1
439 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32
440 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand
441
442 :(scenario check_missing_base_operand_2)
443 % Hide_errors = true;
444 == 0x1
445 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32
446 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
447
448 :(scenario check_base_operand_not_needed_in_direct_mode)
449 == 0x1
450 81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32
451 $error: 0
452
453
454
455 :(code)
456 void check_operands_0f(const line& inst) {
457 assert(inst.words.at(0).data == "0f");
458 if (SIZE(inst.words) == 1) {
459 raise << "opcode '0f' requires a second opcode\n" << end();
460 return;
461 }
462 word op = preprocess_op(inst.words.at(1));
463 if (!contains_key(name_0f, op.data)) {
464 raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
465 return;
466 }
467 check_operands_0f(inst, op);
468 }
469
470 void check_operands_f3(const line& ) {
471 raise << "no supported opcodes starting with f3\n" << end();
472 }
473
474 :(scenario check_missing_disp16_operand)
475 % Hide_errors = true;
476 == 0x1
477
478
479
480 0f 84
481 +error: '0f 84' (jump disp16 bytes away if ZF is set): missing disp16 operand
482
483 :(before "End Globals")
484 map<string, uint8_t> Permitted_operands_0f;
485 :(before "End Init Permitted Operands")
486
487
488
489 put(Permitted_operands_0f, "84", 0x08);
490 put(Permitted_operands_0f, "85", 0x08);
491 put(Permitted_operands_0f, "8c", 0x08);
492 put(Permitted_operands_0f, "8d", 0x08);
493 put(Permitted_operands_0f, "8e", 0x08);
494 put(Permitted_operands_0f, "8f", 0x08);
495
496
497
498
499 put(Permitted_operands_0f, "af", 0x01);
500
501 :(code)
502 void check_operands_0f(const line& inst, const word& op) {
503 uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
504 if (HAS(expected_bitvector, MODRM))
505 check_operands_modrm(inst, op);
506 compare_bitvector_0f(inst, CLEAR(expected_bitvector, MODRM), op);
507 }
508
509 void compare_bitvector_0f(const line& inst, uint8_t expected, const word& op) {
510 if (all_hex_bytes(inst) && has_operands(inst)) return;
511 uint8_t bitvector = compute_operand_bitvector(inst);
512 if (trace_contains_errors()) return;
513 if (bitvector == expected) return;
514 for (int i = 0; i < NUM_OPERAND_TYPES; ++i, bitvector >>= 1, expected >>= 1) {
515
516 if ((bitvector & 0x1) == (expected & 0x1)) continue;
517 const string& optype = Operand_type_name.at(i);
518 if ((bitvector & 0x1) > (expected & 0x1))
519 raise << "'" << to_string(inst) << "' (" << get(name_0f, op.data) << "): unexpected " << optype << " operand\n" << end();
520 else
521 raise << "'" << to_string(inst) << "' (" << get(name_0f, op.data) << "): missing " << optype << " operand\n" << end();
522
523 }
524
525 }
526
527 string tolower(const char* s) {
528 ostringstream out;
529 for (; *s; ++s)
530 out << static_cast<char>(tolower(*s));
531 return out.str();
532 }
533
534
535
536
537
538 :(before "End Includes")
539