1 //: Since we're tagging operands with their types, let's start checking these
  2 //: operand types for each instruction.
  3 
  4 :(scenario check_missing_imm8_operand)
  5 % Hide_errors = true;
  6 == 0x1
  7 cd  # int ??
  8 +error: 'cd' (software interrupt): missing imm8 operand
  9 
 10 :(before "Pack Operands(segment code)")
 11 check_operands(code);
 12 if (trace_contains_errors()) return;
 13 
 14 :(code)
 15 void check_operands(const segment& code) {
 16   trace(99, "transform") << "-- check operands" << end();
 17   for (int i = 0;  i < SIZE(code.lines);  ++i) {
 18     check_operands(code.lines.at(i));
 19     if (trace_contains_errors()) return;  // stop at the first mal-formed instruction
 20   }
 21 }
 22 
 23 void check_operands(const line& inst) {
 24   word op = preprocess_op(inst.words.at(0));
 25   if (op.data == "0f") {
 26     check_operands_0f(inst);
 27     return;
 28   }
 29   if (op.data == "f3") {
 30     check_operands_f3(inst);
 31     return;
 32   }
 33   check_operands(inst, op);
 34 }
 35 
 36 word preprocess_op(word/*copy*/ op) {
 37   op.data = tolower(op.data.c_str());
 38   // opcodes can't be negative
 39   if (starts_with(op.data, "0x"))
 40     op.data = op.data.substr(2);
 41   if (SIZE(op.data) == 1)
 42     op.data = string("0")+op.data;
 43   return op;
 44 }
 45 
 46 void test_preprocess_op() {
 47   word w1;  w1.data = "0xf";
 48   word w2;  w2.data = "0f";
 49   CHECK_EQ(preprocess_op(w1).data, preprocess_op(w2).data);
 50 }
 51 
 52 //: To check the operands for an opcode, we'll track the permitted operands
 53 //: for each supported opcode in a bitvector. That way we can often compute the
 54 //: bitvector for each instruction's operands and compare it with the expected.
 55 
 56 :(before "End Types")
 57 enum operand_type {
 58   // start from the least significant bit
 59   MODRM,  // more complex, may also involve disp8 or disp32
 60   SUBOP,
 61   DISP8,
 62   DISP16,
 63   DISP32,
 64   IMM8,
 65   IMM32,
 66   NUM_OPERAND_TYPES
 67 };
 68 :(before "End Globals")
 69 vector<string> Operand_type_name;
 70 map<string, operand_type> Operand_type;
 71 :(before "End One-time Setup")
 72 init_op_types();
 73 :(code)
 74 void init_op_types() {
 75   assert(NUM_OPERAND_TYPES <= /*bits in a uint8_t*/8);
 76   Operand_type_name.resize(NUM_OPERAND_TYPES);
 77   #define DEF(type) Operand_type_name.at(type) = tolower(#type), put(Operand_type, tolower(#type), type);
 78   DEF(MODRM);
 79   DEF(SUBOP);
 80   DEF(DISP8);
 81   DEF(DISP16);
 82   DEF(DISP32);
 83   DEF(IMM8);
 84   DEF(IMM32);
 85   #undef DEF
 86 }
 87 
 88 :(before "End Globals")
 89 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands;
 90 const uint8_t INVALID_OPERANDS = 0xff;  // no instruction uses all the operand types
 91 :(before "End One-time Setup")
 92 init_permitted_operands();
 93 :(code)
 94 void init_permitted_operands() {
 95   //// Class A: just op, no operands
 96   // halt
 97   put(Permitted_operands, "f4", 0x00);
 98   // inc
 99   put(Permitted_operands, "40", 0x00);
100   put(Permitted_operands, "41", 0x00);
101   put(Permitted_operands, "42", 0x00);
102   put(Permitted_operands, "43", 0x00);
103   put(Permitted_operands, "44", 0x00);
104   put(Permitted_operands, "45", 0x00);
105   put(Permitted_operands, "46", 0x00);
106   put(Permitted_operands, "47", 0x00);
107   // dec
108   put(Permitted_operands, "48", 0x00);
109   put(Permitted_operands, "49", 0x00);
110   put(Permitted_operands, "4a", 0x00);
111   put(Permitted_operands, "4b", 0x00);
112   put(Permitted_operands, "4c", 0x00);
113   put(Permitted_operands, "4d", 0x00);
114   put(Permitted_operands, "4e", 0x00);
115   put(Permitted_operands, "4f", 0x00);
116   // push
117   put(Permitted_operands, "50", 0x00);
118   put(Permitted_operands, "51", 0x00);
119   put(Permitted_operands, "52", 0x00);
120   put(Permitted_operands, "53", 0x00);
121   put(Permitted_operands, "54", 0x00);
122   put(Permitted_operands, "55", 0x00);
123   put(Permitted_operands, "56", 0x00);
124   put(Permitted_operands, "57", 0x00);
125   // pop
126   put(Permitted_operands, "58", 0x00);
127   put(Permitted_operands, "59", 0x00);
128   put(Permitted_operands, "5a", 0x00);
129   put(Permitted_operands, "5b", 0x00);
130   put(Permitted_operands, "5c", 0x00);
131   put(Permitted_operands, "5d", 0x00);
132   put(Permitted_operands, "5e", 0x00);
133   put(Permitted_operands, "5f", 0x00);
134   // return
135   put(Permitted_operands, "c3", 0x00);
136 
137   //// Class B: just op and disp8
138   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
139   //  0     0     0      |0       1     0     0
140 
141   // jump
142   put(Permitted_operands, "eb", 0x04);
143   put(Permitted_operands, "74", 0x04);
144   put(Permitted_operands, "75", 0x04);
145   put(Permitted_operands, "7c", 0x04);
146   put(Permitted_operands, "7d", 0x04);
147   put(Permitted_operands, "7e", 0x04);
148   put(Permitted_operands, "7f", 0x04);
149 
150   //// Class C: just op and disp16
151   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
152   //  0     0     0      |1       0     0     0
153   put(Permitted_operands, "e9", 0x08);  // jump
154 
155   //// Class D: just op and disp32
156   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
157   //  0     0     1      |0       0     0     0
158   put(Permitted_operands, "e8", 0x10);  // call
159 
160   //// Class E: just op and imm8
161   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
162   //  0     1     0      |0       0     0     0
163   put(Permitted_operands, "cd", 0x20);  // software interrupt
164 
165   //// Class F: just op and imm32
166   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
167   //  1     0     0      |0       0     0     0
168   put(Permitted_operands, "05", 0x40);  // add
169   put(Permitted_operands, "2d", 0x40);  // subtract
170   put(Permitted_operands, "25", 0x40);  // and
171   put(Permitted_operands, "0d", 0x40);  // or
172   put(Permitted_operands, "35", 0x40);  // xor
173   put(Permitted_operands, "3d", 0x40);  // compare
174   put(Permitted_operands, "68", 0x40);  // push
175   // copy
176   put(Permitted_operands, "b8", 0x40);
177   put(Permitted_operands, "b9", 0x40);
178   put(Permitted_operands, "ba", 0x40);
179   put(Permitted_operands, "bb", 0x40);
180   put(Permitted_operands, "bc", 0x40);
181   put(Permitted_operands, "bd", 0x40);
182   put(Permitted_operands, "be", 0x40);
183   put(Permitted_operands, "bf", 0x40);
184 
185   //// Class M: using ModR/M byte
186   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
187   //  0     0     0      |0       0     0     1
188 
189   // add
190   put(Permitted_operands, "01", 0x01);
191   put(Permitted_operands, "03", 0x01);
192   // subtract
193   put(Permitted_operands, "29", 0x01);
194   put(Permitted_operands, "2b", 0x01);
195   // and
196   put(Permitted_operands, "21", 0x01);
197   put(Permitted_operands, "23", 0x01);
198   // or
199   put(Permitted_operands, "09", 0x01);
200   put(Permitted_operands, "0b", 0x01);
201   // xor
202   put(Permitted_operands, "31", 0x01);
203   put(Permitted_operands, "33", 0x01);
204   // compare
205   put(Permitted_operands, "39", 0x01);
206   put(Permitted_operands, "3b", 0x01);
207   // copy
208   put(Permitted_operands, "88", 0x01);
209   put(Permitted_operands, "89", 0x01);
210   put(Permitted_operands, "8a", 0x01);
211   put(Permitted_operands, "8b", 0x01);
212   // swap
213   put(Permitted_operands, "87", 0x01);
214   // lea
215   put(Permitted_operands, "8d", 0x01);
216   // pop
217   put(Permitted_operands, "8f", 0x01);
218 
219   //// Class O: op, ModR/M and subop (not r32)
220   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
221   //  0     0     0      |0       0     1     1
222   put(Permitted_operands, "f7", 0x03);  // test/not/mul/div
223   put(Permitted_operands, "ff", 0x03);  // jump/push/call
224 
225   //// Class N: op, ModR/M and imm32
226   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
227   //  1     0     0      |0       0     0     1
228   put(Permitted_operands, "c7", 0x41);  // copy
229 
230   //// Class P: op, ModR/M, subop (not r32) and imm32
231   //  imm32 imm8  disp32 |disp16  disp8 subop modrm
232   //  1     0     0      |0       0     1     1
233   put(Permitted_operands, "81", 0x43);  // combine
234 
235   // End Init Permitted Operands
236 }
237 
238 :(code)
239 #define HAS(bitvector, bit)  ((bitvector) & (1 << (bit)))
240 #define SET(bitvector, bit)  ((bitvector) | (1 << (bit)))
241 #define CLEAR(bitvector, bit)  ((bitvector) & (~(1 << (bit))))
242 
243 void check_operands(const line& inst, const word& op) {
244   if (!is_hex_byte(op)) return;
245   uint8_t expected_bitvector = get(Permitted_operands, op.data);
246   if (HAS(expected_bitvector, MODRM)) {
247     check_operands_modrm(inst, op);
248     compare_bitvector_modrm(inst, expected_bitvector, op);
249   }
250   else {
251     compare_bitvector(inst, expected_bitvector, op);
252   }
253 }
254 
255 //: Many instructions can be checked just by comparing bitvectors.
256 
257 void compare_bitvector(const line& inst, uint8_t expected, const word& op) {
258   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
259   uint8_t bitvector = compute_operand_bitvector(inst);
260   if (trace_contains_errors()) return;  // duplicate operand type
261   if (bitvector == expected) return;  // all good with this instruction
262   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
263 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
264     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
265     const string& optype = Operand_type_name.at(i);
266     if ((bitvector & 0x1) > (expected & 0x1))
267       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
268     else
269       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
270     // continue giving all errors for a single instruction
271   }
272   // ignore settings in any unused bits
273 }
274 
275 string maybe_name(const word& op) {
276   if (!is_hex_byte(op)) return "";
277   if (!contains_key(Name, op.data)) return "";
278   // strip stuff in parens from the name
279   const string& s = get(Name, op.data);
280   return " ("+s.substr(0, s.find(" ("))+')';
281 }
282 
283 uint32_t compute_operand_bitvector(const line& inst) {
284   uint32_t bitvector = 0;
285   for (int i = /*skip op*/1;  i < SIZE(inst.words);  ++i) {
286     bitvector = bitvector | bitvector_for_operand(inst.words.at(i));
287     if (trace_contains_errors()) return INVALID_OPERANDS;  // duplicate operand type
288   }
289   return bitvector;
290 }
291 
292 bool has_operands(const line& inst) {
293   return SIZE(inst.words) > first_operand(inst);
294 }
295 
296 int first_operand(const line& inst) {
297   if (inst.words.at(0).data == "0f") return 2;
298   if (inst.words.at(0).data == "f2" || inst.words.at(0).data == "f3") {
299     if (inst.words.at(1).data == "0f")
300       return 3;
301     else
302       return 2;
303   }
304   return 1;
305 }
306 
307 // Scan the metadata of 'w' and return the bit corresponding to any operand type.
308 // Also raise an error if metadata contains multiple operand types.
309 uint32_t bitvector_for_operand(const word& w) {
310   uint32_t bv = 0;
311   bool found = false;
312   for (int i = 0;  i < SIZE(w.metadata);  ++i) {
313     const string& curr = w.metadata.at(i);
314     if (!contains_key(Operand_type, curr)) continue;  // ignore unrecognized metadata
315     if (found) {
316       raise << "'" << w.original << "' has conflicting operand types; it should have only one\n" << end();
317       return INVALID_OPERANDS;
318     }
319     bv = (1 << get(Operand_type, curr));
320     found = true;
321   }
322   return bv;
323 }
324 
325 :(scenario conflicting_operand_type)
326 % Hide_errors = true;
327 == 0x1
328 cd/software-interrupt 80/imm8/imm32
329 +error: '80/imm8/imm32' has conflicting operand types; it should have only one
330 
331 //: Instructions computing effective addresses have more complex rules, so
332 //: we'll hard-code a common set of instruction-decoding rules.
333 
334 :(scenario check_missing_mod_operand)
335 % Hide_errors = true;
336 == 0x1
337 81 0/add/subop       3/rm32/ebx 1/imm32
338 +error: '81 0/add/subop 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing mod operand
339 
340 :(code)
341 void check_operands_modrm(const line& inst, const word& op) {
342   if (all_hex_bytes(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
343   check_operand_metadata_present(inst, "mod", op);
344   check_operand_metadata_present(inst, "rm32", op);
345   // no check for r32; some instructions don't use it; just assume it's 0 if missing
346   if (op.data == "81" || op.data == "8f" || op.data == "ff") {  // keep sync'd with 'help subop'
347     check_operand_metadata_present(inst, "subop", op);
348     check_operand_metadata_absent(inst, "r32", op, "should be replaced by subop");
349   }
350   if (trace_contains_errors()) return;
351   if (metadata(inst, "rm32").data != "4") return;
352   // SIB byte checks
353   uint8_t mod = hex_byte(metadata(inst, "mod").data);
354   if (mod != /*direct*/3) {
355     check_operand_metadata_present(inst, "base", op);
356     check_operand_metadata_present(inst, "index", op);  // otherwise why go to SIB?
357   }
358   else {
359     check_operand_metadata_absent(inst, "base", op, "direct mode");
360     check_operand_metadata_absent(inst, "index", op, "direct mode");
361   }
362   // no check for scale; 0 (2**0 = 1) by default
363 }
364 
365 // same as compare_bitvector, with a couple of exceptions for modrm-based instructions
366 //   exception 1: ignore modrm bit since we already checked it above
367 //   exception 2: modrm instructions can use a displacement on occasion
368 void compare_bitvector_modrm(const line& inst, uint8_t expected, const word& op) {
369   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
370   uint8_t bitvector = compute_operand_bitvector(inst);
371   if (trace_contains_errors()) return;  // duplicate operand type
372   expected = CLEAR(expected, MODRM);  // exception 1
373   if (bitvector == expected) return;  // all good with this instruction
374   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
375 //?     cerr << "comparing for modrm " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
376     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
377     if (i == DISP8 || i == DISP32) continue;  // exception 2
378     const string& optype = Operand_type_name.at(i);
379     if ((bitvector & 0x1) > (expected & 0x1))
380       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << optype << " operand\n" << end();
381     else
382       raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << optype << " operand\n" << end();
383     // continue giving all errors for a single instruction
384   }
385   // ignore settings in any unused bits
386 }
387 
388 void check_operand_metadata_present(const line& inst, const string& type, const word& op) {
389   if (!has_operand_metadata(inst, type))
390     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": missing " << type << " operand\n" << end();
391 }
392 
393 void check_operand_metadata_absent(const line& inst, const string& type, const word& op, const string& msg) {
394   if (has_operand_metadata(inst, type))
395     raise << "'" << to_string(inst) << "'" << maybe_name(op) << ": unexpected " << type << " operand (" << msg << ")\n" << end();
396 }
397 
398 :(scenarios transform)
399 :(scenario modrm_with_displacement)
400 % Reg[EAX].u = 0x1;
401 == 0x1
402 # just avoid null pointer
403 8b/copy 1/mod/lookup+disp8 0/rm32/EAX 2/r32/EDX 4/disp8  # copy *(EAX+4) to EDX
404 $error: 0
405 :(scenarios run)
406 
407 :(scenario conflicting_operands_in_modrm_instruction)
408 % Hide_errors = true;
409 == 0x1
410 01/add 0/mod 3/mod
411 +error: '01/add 0/mod 3/mod' has conflicting mod operands
412 
413 :(scenario conflicting_operand_type_modrm)
414 % Hide_errors = true;
415 == 0x1
416 01/add 0/mod 3/rm32/r32
417 +error: '3/rm32/r32' has conflicting operand types; it should have only one
418 
419 :(scenario check_missing_rm32_operand)
420 % Hide_errors = true;
421 == 0x1
422 81 0/add/subop 0/mod            1/imm32
423 +error: '81 0/add/subop 0/mod 1/imm32' (combine rm32 with imm32 based on subop): missing rm32 operand
424 
425 :(scenario check_missing_subop_operand)
426 % Hide_errors = true;
427 == 0x1
428 81             0/mod 3/rm32/ebx 1/imm32
429 +error: '81 0/mod 3/rm32/ebx 1/imm32' (combine rm32 with imm32 based on subop): missing subop operand
430 
431 :(scenario check_missing_base_operand)
432 % Hide_errors = true;
433 == 0x1
434 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32
435 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
436 
437 :(scenario check_missing_index_operand)
438 % Hide_errors = true;
439 == 0x1
440 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32
441 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 0/base 1/imm32' (combine rm32 with imm32 based on subop): missing index operand
442 
443 :(scenario check_missing_base_operand_2)
444 % Hide_errors = true;
445 == 0x1
446 81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32
447 +error: '81 0/add/subop 0/mod/indirect 4/rm32/use-sib 2/index 3/scale 1/imm32' (combine rm32 with imm32 based on subop): missing base operand
448 
449 :(scenario check_base_operand_not_needed_in_direct_mode)
450 == 0x1
451 81 0/add/subop 3/mod/indirect 4/rm32/use-sib 1/imm32
452 $error: 0
453 
454 //:: similarly handle multi-byte opcodes
455 
456 :(code)
457 void check_operands_0f(const line& inst) {
458   assert(inst.words.at(0).data == "0f");
459   if (SIZE(inst.words) == 1) {
460     raise << "opcode '0f' requires a second opcode\n" << end();
461     return;
462   }
463   word op = preprocess_op(inst.words.at(1));
464   if (!contains_key(Name_0f, op.data)) {
465     raise << "unknown 2-byte opcode '0f " << op.data << "'\n" << end();
466     return;
467   }
468   check_operands_0f(inst, op);
469 }
470 
471 void check_operands_f3(const line& /*unused*/) {
472   raise << "no supported opcodes starting with f3\n" << end();
473 }
474 
475 :(scenario check_missing_disp16_operand)
476 % Hide_errors = true;
477 == 0x1
478 # instruction                     effective address                                                   operand     displacement    immediate
479 # op          subop               mod             rm32          base        index         scale       r32
480 # 1-3 bytes   3 bits              2 bits          3 bits        3 bits      3 bits        2 bits      2 bits      0/1/2/4 bytes   0/1/2/4 bytes
481   0f 84                                                                                                                                             # jmp if ZF to ??
482 +error: '0f 84' (jump disp16 bytes away if equal, if ZF is set): missing disp16 operand
483 
484 :(before "End Globals")
485 map</*op*/string, /*bitvector*/uint8_t> Permitted_operands_0f;
486 :(before "End Init Permitted Operands")
487 //// Class C: just op and disp16
488 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
489 //  0     0     0      |1       0     0     0
490 put_new(Permitted_operands_0f, "84", 0x08);
491 put_new(Permitted_operands_0f, "85", 0x08);
492 put_new(Permitted_operands_0f, "8c", 0x08);
493 put_new(Permitted_operands_0f, "8d", 0x08);
494 put_new(Permitted_operands_0f, "8e", 0x08);
495 put_new(Permitted_operands_0f, "8f", 0x08);
496 
497 //// Class M: using ModR/M byte
498 //  imm32 imm8  disp32 |disp16  disp8 subop modrm
499 //  0     0     0      |0       0     0     1
500 put_new(Permitted_operands_0f, "af", 0x01);
501 
502 :(code)
503 void check_operands_0f(const line& inst, const word& op) {
504   uint8_t expected_bitvector = get(Permitted_operands_0f, op.data);
505   if (HAS(expected_bitvector, MODRM))
506     check_operands_modrm(inst, op);
507   compare_bitvector_0f(inst, CLEAR(expected_bitvector, MODRM), op);
508 }
509 
510 void compare_bitvector_0f(const line& inst, uint8_t expected, const word& op) {
511   if (all_hex_bytes(inst) && has_operands(inst)) return;  // deliberately programming in raw hex; we'll raise a warning elsewhere
512   uint8_t bitvector = compute_operand_bitvector(inst);
513   if (trace_contains_errors()) return;  // duplicate operand type
514   if (bitvector == expected) return;  // all good with this instruction
515   for (int i = 0;  i < NUM_OPERAND_TYPES;  ++i, bitvector >>= 1, expected >>= 1) {
516 //?     cerr << "comparing " << HEXBYTE << NUM(bitvector) << " with " << NUM(expected) << '\n';
517     if ((bitvector & 0x1) == (expected & 0x1)) continue;  // all good with this operand
518     const string& optype = Operand_type_name.at(i);
519     if ((bitvector & 0x1) > (expected & 0x1))
520       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": unexpected " << optype << " operand\n" << end();
521     else
522       raise << "'" << to_string(inst) << "'" << maybe_name_0f(op) << ": missing " << optype << " operand\n" << end();
523     // continue giving all errors for a single instruction
524   }
525   // ignore settings in any unused bits
526 }
527 
528 string maybe_name_0f(const word& op) {
529   if (!is_hex_byte(op)) return "";
530   if (!contains_key(Name_0f, op.data)) return "";
531   // strip stuff in parens from the name
532   const string& s = get(Name_0f, op.data);
533   return " ("+s.substr(0, s.find(" ("))+')';
534 }
535 
536 string tolower(const char* s) {
537   ostringstream out;
538   for (/*nada*/;  *s;  ++s)
539     out << static_cast<char>(tolower(*s));
540   return out.str();
541 }
542 
543 #undef HAS
544 #undef SET
545 #undef CLEAR
546 
547 :(before "End Includes")
548 #include<cctype>