From 059c5ab9a67e2ddf45fffc792bcc53b177c87dfe Mon Sep 17 00:00:00 2001 From: Crystal Date: Sat, 24 Feb 2024 18:23:19 +0100 Subject: Add stuff --- blog/asm/1.html | 134 +++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 118 insertions(+), 16 deletions(-) (limited to 'blog') diff --git a/blog/asm/1.html b/blog/asm/1.html index e9efd34..f283a63 100644 --- a/blog/asm/1.html +++ b/blog/asm/1.html @@ -3,7 +3,7 @@ "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd"> - + x86 Assembly from my understanding @@ -23,9 +23,9 @@

Soooo this article (or maybe even a series of articles, who knows ?) will be about x86 assembly, or rather, what I understood from it and my road from the bottom-up hopefully reaching a good level of understanding

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Memory :

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Memory :

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Memory is a sequence of octets (Aka 8bits) that each have a unique integer assigned to them called The Effective Address (EA), in this particular CPU Architecture (the i8086), the octet is designated by a couple (A segment number, and the offset in the segment)

@@ -40,9 +40,9 @@ Memory is a sequence of octets (Aka 8bits) that each have a unique integer assig The offset and segment are encoded in 16bits, so they take a value between 0 and 65535

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Important :

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Important :

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The relation between the Effective Address and the Segment & Offset is as follow :

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  • Example :
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  • Example :
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    Let the Physical address (Or Effective Address, these two terms are enterchangeable) 12345h (the h refers to Hexadecimal, which can also be written like this 0x12345), the register DS = 1230h and the register SI = 0045h, the CPU calculates the physical address by multiplying the content of the segment register DS by 10h (or 16) and adding the content of the register SI. so we get : 1230h x 10h + 45h = 12345h

    @@ -66,16 +66,16 @@ Now if you are a clever one ( I know you are, since you are reading this <3 )
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Registers

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Registers

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The 8086 CPU has 14 registers of 16bits of size. From the POV of the user, the 8086 has 3 groups of 4 registers of 16bits. One state register of 9bits and a counting program of 16bits inaccessible to the user (whatever this means).

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General Registers

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General Registers

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General registers contribute to arithmetic’s and logic and addressing too.

@@ -106,6 +106,108 @@ Now here are the Registers we can find in this section: 
MOV BL, [500] ;(BL = 500H)
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+CX: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL to also perform 8-bit instructions. It is used in looping and rotation. Example: +

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MOV CX, 0005
+LOOP
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+DX: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to also perform 8-bit instructions. It is used in the multiplication and input/output port addressing. Example: +

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MUL BX (DX, AX = AX * BX)
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Offset/Address Registers

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+SP: This is the stack pointer. It is of 16 bits. It points to the topmost item of the stack. If the stack is empty the stack pointer will be (FFFE)H (or 65534 in decimal). Its offset address is relative to the stack segment(SS). +

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+BP: This is the base pointer. It is of 16 bits. It is primarily used in accessing parameters passed by the stack. Its offset address is relative to the stack segment(SS). +

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+SI: This is the source index register. It is of 16 bits. It is used in the pointer addressing of data and as a source in some string-related operations. Its offset is relative to the data segment(DS). +

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+DI: This is the destination index register. It is of 16 bits. It is used in the pointer addressing of data and as a destination in some string-related operations. Its offset is relative to the extra segment(ES). +

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Segment Registers

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+CS: Code Segment, it defines the start of the program memory, and the different addresses of the different instructions relative to CS. +

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+DS: Data Segment, defines the start of the data memory where we store all data processed by the program. +

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+SS: Stack Segment, or the start of the pile. The pile is a memory zone that is managed in a particular way, it’s like a pile of plates, where we can only remove and add plates on top of the pile. Only one address register is enough to manage it, its the stack pointer SP. We say that this pile is a LIFO pile (Last IN, First OUT) +

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+EX: The start of an auxiliary segment for data +

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The format of an address:

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+An Address must have this fellowing form [RS : RO] with the following possibilities: +

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  • A value : Nothing
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  • ES : DI
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  • CS : SI
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  • ES : BP
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  • DS : BX
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Note 1 :

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+When the register isn’t specified. the CPU adds it depending on the offset used : +

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  • If the offset is : DI SI or BX, the Segment used is DS.
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  • If its BP, then the segment is SS.
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Note 2 :

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+Apparently we will assume that we are in the DS segment and only access to memory using the offset. +

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Note 3 :

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+The values of the registers CS DS and SS are automatically initialized by the OS when launching the program. So these segments are implicit. AKA : If we want to access a specific data in memory, we just need to specify its offset. +

@@ -113,7 +215,7 @@ Now here are the Registers we can find in this section:

Author: Crystal

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Created: 2024-02-24 Sat 17:36

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Created: 2024-02-24 Sat 18:22

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