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authorflywind <xzsflywind@gmail.com>2021-04-29 19:39:36 +0800
committerGitHub <noreply@github.com>2021-04-29 13:39:36 +0200
commit5edddd68d04648553bc02d52cd53d3a1a14102f3 (patch)
tree0a50c544369fcca5e063de23df6d0ad390d0a371
parent87229e272ecd4012b750215d35e914580cd8475c (diff)
downloadNim-5edddd68d04648553bc02d52cd53d3a1a14102f3.tar.gz
improve cache line size (#17885)
* improve cache line size

- 64bit system tend to use cache line of 64 bytes
- add align

https://trishagee.com/2011/07/22/dissecting_the_disruptor_why_its_so_fast_part_two__magic_cache_line_padding


Though I'm not sure, what do you think? @timotheecour

* Update lib/pure/concurrency/threadpool.nim
-rw-r--r--lib/pure/concurrency/threadpool.nim9
1 files changed, 3 insertions, 6 deletions
diff --git a/lib/pure/concurrency/threadpool.nim b/lib/pure/concurrency/threadpool.nim
index 9beb39522..f8a5f9ba8 100644
--- a/lib/pure/concurrency/threadpool.nim
+++ b/lib/pure/concurrency/threadpool.nim
@@ -52,17 +52,14 @@ proc signal(cv: var Semaphore) =
   release(cv.L)
   signal(cv.c)
 
-const CacheLineSize = 32 # true for most archs
+const CacheLineSize = 64 # true for most archs
 
 type
   Barrier {.compilerproc.} = object
     entered: int
     cv: Semaphore # Semaphore takes 3 words at least
-    when sizeof(int) < 8:
-      cacheAlign: array[CacheLineSize-4*sizeof(int), byte]
-    left: int
-    cacheAlign2: array[CacheLineSize-sizeof(int), byte]
-    interest: bool # whether the master is interested in the "all done" event
+    left {.align(CacheLineSize).}: int
+    interest {.align(CacheLineSize).} : bool # whether the master is interested in the "all done" event
 
 proc barrierEnter(b: ptr Barrier) {.compilerproc, inline.} =
   # due to the signaling between threads, it is ensured we are the only