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authorAraq <rumpf_a@web.de>2018-02-28 10:01:18 +0100
committerAraq <rumpf_a@web.de>2018-02-28 10:13:55 +0100
commit934bba5255cd73d31513b824b1cdf9dcc1738111 (patch)
treebc8e13df9c61a33392e640b694c51b0a30d185dc /compiler/vm.nim
parenta897371797154844f96906e72fa013b8205d0393 (diff)
downloadNim-934bba5255cd73d31513b824b1cdf9dcc1738111.tar.gz
some progress on #7261; VM does not support the new backwards indexing
Diffstat (limited to 'compiler/vm.nim')
-rw-r--r--compiler/vm.nim18
1 files changed, 15 insertions, 3 deletions
diff --git a/compiler/vm.nim b/compiler/vm.nim
index 0a706b0fc..23216f0a3 100644
--- a/compiler/vm.nim
+++ b/compiler/vm.nim
@@ -779,9 +779,21 @@ proc rawExecute(c: PCtx, start: int, tos: PStackFrame): TFullReg =
       regs[ra].intVal = ord(regs[rb].intVal <% regs[rc].intVal)
     of opcEqRef:
       decodeBC(rkInt)
-      regs[ra].intVal = ord((regs[rb].node.kind == nkNilLit and
-                             regs[rc].node.kind == nkNilLit) or
-                             regs[rb].node == regs[rc].node)
+      if regs[rb].kind == rkNodeAddr:
+        if regs[rc].kind == rkNodeAddr:
+          regs[ra].intVal = ord(regs[rb].nodeAddr == regs[rc].nodeAddr)
+        else:
+          assert regs[rc].kind == rkNode
+          # we know these cannot be equal
+          regs[ra].intVal = ord(false)
+      elif regs[rc].kind == rkNodeAddr:
+        assert regs[rb].kind == rkNode
+        # we know these cannot be equal
+        regs[ra].intVal = ord(false)
+      else:
+        regs[ra].intVal = ord((regs[rb].node.kind == nkNilLit and
+                              regs[rc].node.kind == nkNilLit) or
+                              regs[rb].node == regs[rc].node)
     of opcEqNimrodNode:
       decodeBC(rkInt)
       regs[ra].intVal =