diff options
| author | Andreas Rumpf <rumpf_a@web.de> | 2016-07-30 16:28:58 +0200 |
|---|---|---|
| committer | Andreas Rumpf <rumpf_a@web.de> | 2016-07-30 16:34:42 +0200 |
| commit | 39ebe2175bd4e8e62d03875d06b24feafd36f8f7 (patch) | |
| tree | e27cc59112675e052c70c6063f6bcca8e29e103c /compiler/vmgen.nim | |
| parent | 8876ed23f1dc6d12a8ae7bf061b7e31c3adf54b4 (diff) | |
| download | Nim-39ebe2175bd4e8e62d03875d06b24feafd36f8f7.tar.gz | |
compiler almost free of deprecated expr/stmt names
Diffstat (limited to 'compiler/vmgen.nim')
| -rw-r--r-- | compiler/vmgen.nim | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/vmgen.nim b/compiler/vmgen.nim index 8991c238f..366662258 100644 --- a/compiler/vmgen.nim +++ b/compiler/vmgen.nim @@ -1266,7 +1266,7 @@ proc checkCanEval(c: PCtx; n: PNode) = proc isTemp(c: PCtx; dest: TDest): bool = result = dest >= 0 and c.prc.slots[dest].kind >= slotTempUnknown -template needsAdditionalCopy(n): expr = +template needsAdditionalCopy(n): untyped = not c.isTemp(dest) and not fitsRegister(n.typ) proc skipDeref(n: PNode): PNode = @@ -1404,7 +1404,7 @@ proc genRdVar(c: PCtx; n: PNode; dest: var TDest; flags: TGenFlags) = # see tests/t99bott for an example that triggers it: cannotEval(n) -template needsRegLoad(): expr = +template needsRegLoad(): untyped = gfAddrOf notin flags and fitsRegister(n.typ.skipTypes({tyVar})) proc genArrAccess2(c: PCtx; n: PNode; dest: var TDest; opc: TOpcode; |