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author | Andrii Riabushenko <cdome@bk.ru> | 2018-10-24 11:24:23 +0100 |
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committer | Andrii Riabushenko <cdome@bk.ru> | 2018-10-24 11:24:23 +0100 |
commit | a7c9533a73ea536014e279e39272995840400830 (patch) | |
tree | bb45a8cd84677fb7f464d8672fa78e6490ac9c67 /compiler | |
parent | 72370c8dfab35b46c8aa5f1647d8c7a61b85a68e (diff) | |
download | Nim-a7c9533a73ea536014e279e39272995840400830.tar.gz |
Add int float casts to vm
Diffstat (limited to 'compiler')
-rw-r--r-- | compiler/vm.nim | 12 | ||||
-rw-r--r-- | compiler/vmdef.nim | 4 | ||||
-rw-r--r-- | compiler/vmgen.nim | 27 |
3 files changed, 40 insertions, 3 deletions
diff --git a/compiler/vm.nim b/compiler/vm.nim index 420934470..848cbfcf0 100644 --- a/compiler/vm.nim +++ b/compiler/vm.nim @@ -488,6 +488,18 @@ proc rawExecute(c: PCtx, start: int, tos: PStackFrame): TFullReg = of opcAsgnFloat: decodeB(rkFloat) regs[ra].floatVal = regs[rb].floatVal + of opcAsgnIntFromFloat32: + decodeB(rkFloat) + regs[ra].intVal = cast[int32](float32(regs[rb].floatVal)) + of opcAsgnIntFromFloat64: + decodeB(rkFloat) + regs[ra].intVal = cast[int64](regs[rb].floatVal) + of opcAsgnFloat32FromInt: + decodeB(rkInt) + regs[ra].floatVal = cast[float32](int32(regs[rb].intVal)) + of opcAsgnFloat64FromInt: + decodeB(rkInt) + regs[ra].floatVal = cast[float64](int64(regs[rb].intVal)) of opcAsgnComplex: asgnComplex(regs[ra], regs[instr.regB]) of opcAsgnRef: diff --git a/compiler/vmdef.nim b/compiler/vmdef.nim index 875ae5a52..25ace3cdd 100644 --- a/compiler/vmdef.nim +++ b/compiler/vmdef.nim @@ -35,6 +35,10 @@ type opcAsgnStr, opcAsgnFloat, opcAsgnRef, + opcAsgnIntFromFloat32, # int and float must be of the same byte size + opcAsgnIntFromFloat64, # int and float must be of the same byte size + opcAsgnFloat32FromInt, # int and float must be of the same byte size + opcAsgnFloat64FromInt, # int and float must be of the same byte size opcAsgnComplex, opcNodeToReg, diff --git a/compiler/vmgen.nim b/compiler/vmgen.nim index c59581aca..26efea683 100644 --- a/compiler/vmgen.nim +++ b/compiler/vmgen.nim @@ -769,7 +769,7 @@ proc genCard(c: PCtx; n: PNode; dest: var TDest) = c.gABC(n, opcCard, dest, tmp) c.freeTemp(tmp) -proc genIntCast(c: PCtx; n: PNode; dest: var TDest) = +proc genCastIntFloat(c: PCtx; n: PNode; dest: var TDest) = const allowedIntegers = {tyInt..tyInt64, tyUInt..tyUInt64, tyChar} var signedIntegers = {tyInt8..tyInt32} var unsignedIntegers = {tyUInt8..tyUInt32, tyChar} @@ -809,8 +809,29 @@ proc genIntCast(c: PCtx; n: PNode; dest: var TDest) = c.freeTemp(tmp) c.freeTemp(tmp2) c.freeTemp(tmp3) + elif src_size == getSize(c.config, dst) and src.kind in allowedIntegers and + dst.kind in {tyFloat, tyFloat32, tyFloat64}: + + let tmp = c.getTemp(n.sons[1].typ) + if dest < 0: dest = c.getTemp(n[0].typ) + if dst.kind == tyFloat32: + c.gABC(n, opcAsgnFloat32FromInt, dest, tmp) + else: + c.gABC(n, opcAsgnFloat64FromInt, dest, tmp) + c.freeTemp(tmp) + + elif src_size == getSize(c.config, dst) and src.kind in {tyFloat, tyFloat32, tyFloat64} and + dst.kind in allowedIntegers: + + let tmp = c.getTemp(n.sons[1].typ) + if dest < 0: dest = c.getTemp(n[0].typ) + if src.kind == tyFloat32: + c.gABC(n, opcAsgnIntFromFloat32, dest, tmp) + else: + c.gABC(n, opcAsgnIntFromFloat64, dest, tmp) + c.freeTemp(tmp) else: - globalError(c.config, n.info, "VM is only allowed to 'cast' between integers of same size") + globalError(c.config, n.info, "VM is only allowed to 'cast' between integers and/or floats of same size") proc genVoidABC(c: PCtx, n: PNode, dest: TDest, opcode: TOpcode) = unused(c, n, dest) @@ -2008,7 +2029,7 @@ proc gen(c: PCtx; n: PNode; dest: var TDest; flags: TGenFlags = {}) = if allowCast in c.features: genConv(c, n, n.sons[1], dest, opcCast) else: - genIntCast(c, n, dest) + genCastIntFloat(c, n, dest) of nkTypeOfExpr: genTypeLit(c, n.typ, dest) of nkComesFrom: |