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authorKartik Agaram <vc@akkartik.com>2020-03-06 18:31:14 -0800
committerKartik Agaram <vc@akkartik.com>2020-03-06 18:34:27 -0800
commit8f256f1f2ee6a2a49816dd23d26cd120f526bf0b (patch)
tree314294998b527980cdf85ecb51386642bfbe3af4 /013direct_addressing.cc
parent4c19dd3968d2ce733073774867d97cc96b4277e6 (diff)
downloadmu-8f256f1f2ee6a2a49816dd23d26cd120f526bf0b.tar.gz
6090 - new instruction: multiply by immediate
This is a 3-operand instruction:
  r32 = rm32 * imm32

It looks like https://c9x.me/x86/html/file_module_x86_id_138.html has a
bug, implying the same opcode supports a 2-operand version. I don't see
that in the Intel manual pdf, or at alternative sites like https://www.felixcloutier.com/x86/imul

Native runs seem to validate my understanding.

In the process I also fixed a bug in the existing multiply instruction
0f af: the only flags it sets are OF and CF. The other existing multiply
instruction f7 was doing things right.
Diffstat (limited to '013direct_addressing.cc')
-rw-r--r--013direct_addressing.cc4
1 files changed, 1 insertions, 3 deletions
diff --git a/013direct_addressing.cc b/013direct_addressing.cc
index 729b4d08..2450e54c 100644
--- a/013direct_addressing.cc
+++ b/013direct_addressing.cc
@@ -321,10 +321,8 @@ case 0xaf: {  // multiply r32 by r/m32
   trace(Callstack_depth+1, "run") << "multiply " << rname(arg1) << " by r/m32" << end();
   const int32_t* arg2 = effective_address(modrm);
   int32_t result = Reg[arg1].i * (*arg2);
-  SF = (Reg[arg1].i < 0);
-  ZF = (Reg[arg1].i == 0);
   int64_t full_result = static_cast<int64_t>(Reg[arg1].i) * (*arg2);
-  OF = (Reg[arg1].i != full_result);
+  OF = (result != full_result);
   CF = OF;
   trace(Callstack_depth+1, "run") << "SF=" << SF << "; ZF=" << ZF << "; CF=" << CF << "; OF=" << OF << end();
   Reg[arg1].i = result;