diff options
| author | Kartik K. Agaram <vc@akkartik.com> | 2017-10-13 01:27:51 -0700 |
|---|---|---|
| committer | Kartik K. Agaram <vc@akkartik.com> | 2017-10-13 01:27:51 -0700 |
| commit | ba2ec7250d4060e8ebf4a54c31f87d03ab9d8e27 (patch) | |
| tree | a359c7841f16f12d4e78dd47168a092dc410f999 | |
| parent | 5a25c6e66f78b0c5588af9de8d42e30e0d2232f3 (diff) | |
| download | mu-ba2ec7250d4060e8ebf4a54c31f87d03ab9d8e27.tar.gz | |
4059
| -rw-r--r-- | html/subx/011direct_addressing.cc.html | 231 | ||||
| -rw-r--r-- | html/subx/012indirect_addressing.cc.html | 295 | ||||
| -rw-r--r-- | html/subx/013immediate_addressing.cc.html | 325 |
3 files changed, 609 insertions, 242 deletions
diff --git a/html/subx/011direct_addressing.cc.html b/html/subx/011direct_addressing.cc.html index 42dd9ea1..97745fd0 100644 --- a/html/subx/011direct_addressing.cc.html +++ b/html/subx/011direct_addressing.cc.html @@ -15,19 +15,20 @@ body { font-size: 12pt; font-family: monospace; color: #aaaaaa; background-color a { color:#eeeeee; text-decoration: none; } a:hover { text-decoration: underline; } * { font-size: 12pt; font-size: 1em; } -.Constant { color: #00a0a0; } -.Special { color: #c00000; } -.Conceal { color: #4e4e4e; } .SalientComment { color: #00ffff; } -.Comment { color: #9090ff; } -.Comment a { color:#0000ee; text-decoration:underline; } -.Delimiter { color: #800080; } .LineNr { color: #444444; } -.Identifier { color: #c0a020; } +.Error { color: #ffffff; background-color: #ff6060; padding-bottom: 1px; } +.Delimiter { color: #800080; } .Normal { color: #aaaaaa; background-color: #080808; padding-bottom: 1px; } -.PreProc { color: #800080; } .cSpecial { color: #008000; } +.Conceal { color: #4e4e4e; } +.Comment { color: #9090ff; } +.Comment a { color:#0000ee; text-decoration:underline; } +.Constant { color: #00a0a0; } +.Special { color: #c00000; } +.Identifier { color: #c0a020; } .traceContains { color: #008000; } +.PreProc { color: #800080; } --> </style> @@ -62,70 +63,156 @@ if ('onhashchange' in window) { </head> <body onload='JumpToLine();'> <pre id='vimCodeElement'> -<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: operating directly on a register</span> -<span id="L2" class="LineNr"> 2 </span> -<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_r32_to_r32)</span> -<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[0].i = 0x10;</span> -<span id="L5" class="LineNr"> 5 </span><span class="Special">% Reg[3].i = 1;</span> -<span id="L6" class="LineNr"> 6 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L7" class="LineNr"> 7 </span> <span class="PreProc">0</span><span class="Constant">1</span> d8 <span class="Comment"># add EBX (reg 3) to EAX (reg 0)</span> -<span id="L8" class="LineNr"> 8 </span><span class="traceContains">+run: add <a href='010core.cc.html#L15'>reg</a> 3 to effective address</span> -<span id="L9" class="LineNr"> 9 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> -<span id="L10" class="LineNr">10 </span><span class="traceContains">+run: storing 0x00000011</span> -<span id="L11" class="LineNr">11 </span> -<span id="L12" class="LineNr">12 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L13" class="LineNr">13 </span><span class="Normal">case</span> <span class="Constant">0x01</span>: <span class="Delimiter">{</span> <span class="Comment">// add r32 to r/m32</span> -<span id="L14" class="LineNr">14 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> -<span id="L15" class="LineNr">15 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> -<span id="L16" class="LineNr">16 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"add <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" to effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L17" class="LineNr">17 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> -<span id="L18" class="LineNr">18 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">);</span> -<span id="L19" class="LineNr">19 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L20" class="LineNr">20 </span><span class="Delimiter">}</span> -<span id="L21" class="LineNr">21 </span> -<span id="L22" class="LineNr">22 </span><span class="Delimiter">:(code)</span> -<span id="L23" class="LineNr">23 </span><span class="Comment">// Implement tables 2-2 and 2-3 in the Intel manual, Volume 2.</span> -<span id="L24" class="LineNr">24 </span><span class="Comment">// We return a pointer so that instructions can write to multiple bytes in</span> -<span id="L25" class="LineNr">25 </span><span class="Comment">// 'Mem' at once.</span> -<span id="L26" class="LineNr">26 </span><span class="Normal">int32_t</span>* <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span><span class="Normal">uint8_t</span> modrm<span class="Delimiter">)</span> <span class="Delimiter">{</span> -<span id="L27" class="LineNr">27 </span> <span class="Normal">uint8_t</span> mod = <span class="Delimiter">(</span>modrm>><span class="Constant">6</span><span class="Delimiter">);</span> -<span id="L28" class="LineNr">28 </span> <span class="Comment">// ignore middle 3 'reg opcode' bits</span> -<span id="L29" class="LineNr">29 </span> <span class="Normal">uint8_t</span> rm = modrm & <span class="Constant">0x7</span><span class="Delimiter">;</span> -<span id="L30" class="LineNr">30 </span> <span class="Normal">int32_t</span>* result = <span class="Constant">0</span><span class="Delimiter">;</span> -<span id="L31" class="LineNr">31 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>mod<span class="Delimiter">)</span> <span class="Delimiter">{</span> -<span id="L32" class="LineNr">32 </span> <span class="Normal">case</span> <span class="Constant">3</span>: -<span id="L33" class="LineNr">33 </span> <span class="Conceal">¦</span> <span class="Comment">// mod 3 is just register direct addressing</span> -<span id="L34" class="LineNr">34 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"effective address is <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>rm<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L35" class="LineNr">35 </span> <span class="Conceal">¦</span> result = &Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">;</span> -<span id="L36" class="LineNr">36 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L37" class="LineNr">37 </span> <span class="Comment">// End Mod Special-cases</span> -<span id="L38" class="LineNr">38 </span> <span class="Normal">default</span>: -<span id="L39" class="LineNr">39 </span> <span class="Conceal">¦</span> cerr << <span class="Constant">"unrecognized mod bits: "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>mod<span class="Delimiter">)</span> << <span class="cSpecial">'\n'</span><span class="Delimiter">;</span> -<span id="L40" class="LineNr">40 </span> <span class="Conceal">¦</span> exit<span class="Delimiter">(</span><span class="Constant">1</span><span class="Delimiter">);</span> -<span id="L41" class="LineNr">41 </span> <span class="Delimiter">}</span> -<span id="L42" class="LineNr">42 </span> <span class="Identifier">return</span> result<span class="Delimiter">;</span> -<span id="L43" class="LineNr">43 </span><span class="Delimiter">}</span> -<span id="L44" class="LineNr">44 </span> -<span id="L45" class="LineNr">45 </span><span class="SalientComment">//:: subtract</span> -<span id="L46" class="LineNr">46 </span> -<span id="L47" class="LineNr">47 </span><span class="Delimiter">:(scenario subtract_r32_from_r32)</span> -<span id="L48" class="LineNr">48 </span><span class="Special">% Reg[0].i = 10;</span> -<span id="L49" class="LineNr">49 </span><span class="Special">% Reg[3].i = 1;</span> -<span id="L50" class="LineNr">50 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L51" class="LineNr">51 </span> <span class="Constant">29</span> d8 <span class="Comment"># subtract EBX (reg 3) from EAX (reg 0)</span> -<span id="L52" class="LineNr">52 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L15'>reg</a> 3 from effective address</span> -<span id="L53" class="LineNr">53 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> -<span id="L54" class="LineNr">54 </span><span class="traceContains">+run: storing 0x00000009</span> -<span id="L55" class="LineNr">55 </span> -<span id="L56" class="LineNr">56 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L57" class="LineNr">57 </span><span class="Normal">case</span> <span class="Constant">0x29</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract r32 from r/m32</span> -<span id="L58" class="LineNr">58 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> -<span id="L59" class="LineNr">59 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> -<span id="L60" class="LineNr">60 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" from effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L61" class="LineNr">61 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> -<span id="L62" class="LineNr">62 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">);</span> -<span id="L63" class="LineNr">63 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L64" class="LineNr">64 </span><span class="Delimiter">}</span> +<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: operating directly on a register</span> +<span id="L2" class="LineNr"> 2 </span> +<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_r32_to_r32)</span> +<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[0].i = 0x10;</span> +<span id="L5" class="LineNr"> 5 </span><span class="Special">% Reg[3].i = 1;</span> +<span id="L6" class="LineNr"> 6 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L7" class="LineNr"> 7 </span> <span class="PreProc">0</span><span class="Constant">1</span> d8 <span class="Comment"># add EBX (reg 3) to EAX (reg 0)</span> +<span id="L8" class="LineNr"> 8 </span><span class="traceContains">+run: add <a href='010core.cc.html#L15'>reg</a> 3 to effective address</span> +<span id="L9" class="LineNr"> 9 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> +<span id="L10" class="LineNr"> 10 </span><span class="traceContains">+run: storing 0x00000011</span> +<span id="L11" class="LineNr"> 11 </span> +<span id="L12" class="LineNr"> 12 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L13" class="LineNr"> 13 </span><span class="Normal">case</span> <span class="Constant">0x01</span>: <span class="Delimiter">{</span> <span class="Comment">// add r32 to r/m32</span> +<span id="L14" class="LineNr"> 14 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L15" class="LineNr"> 15 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L16" class="LineNr"> 16 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"add <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" to effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L17" class="LineNr"> 17 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L18" class="LineNr"> 18 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">);</span> +<span id="L19" class="LineNr"> 19 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L20" class="LineNr"> 20 </span><span class="Delimiter">}</span> +<span id="L21" class="LineNr"> 21 </span> +<span id="L22" class="LineNr"> 22 </span><span class="Delimiter">:(code)</span> +<span id="L23" class="LineNr"> 23 </span><span class="Comment">// Implement tables 2-2 and 2-3 in the Intel manual, Volume 2.</span> +<span id="L24" class="LineNr"> 24 </span><span class="Comment">// We return a pointer so that instructions can write to multiple bytes in</span> +<span id="L25" class="LineNr"> 25 </span><span class="Comment">// 'Mem' at once.</span> +<span id="L26" class="LineNr"> 26 </span><span class="Normal">int32_t</span>* <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span><span class="Normal">uint8_t</span> modrm<span class="Delimiter">)</span> <span class="Delimiter">{</span> +<span id="L27" class="LineNr"> 27 </span> <span class="Normal">uint8_t</span> mod = <span class="Delimiter">(</span>modrm>><span class="Constant">6</span><span class="Delimiter">);</span> +<span id="L28" class="LineNr"> 28 </span> <span class="Comment">// ignore middle 3 'reg opcode' bits</span> +<span id="L29" class="LineNr"> 29 </span> <span class="Normal">uint8_t</span> rm = modrm & <span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L30" class="LineNr"> 30 </span> <span class="Normal">int32_t</span>* result = <span class="Constant">0</span><span class="Delimiter">;</span> +<span id="L31" class="LineNr"> 31 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>mod<span class="Delimiter">)</span> <span class="Delimiter">{</span> +<span id="L32" class="LineNr"> 32 </span> <span class="Normal">case</span> <span class="Constant">3</span>: +<span id="L33" class="LineNr"> 33 </span> <span class="Conceal">¦</span> <span class="Comment">// mod 3 is just register direct addressing</span> +<span id="L34" class="LineNr"> 34 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"effective address is <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>rm<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L35" class="LineNr"> 35 </span> <span class="Conceal">¦</span> result = &Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">;</span> +<span id="L36" class="LineNr"> 36 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L37" class="LineNr"> 37 </span> <span class="Comment">// End Mod Special-cases</span> +<span id="L38" class="LineNr"> 38 </span> <span class="Normal">default</span>: +<span id="L39" class="LineNr"> 39 </span> <span class="Conceal">¦</span> cerr << <span class="Constant">"unrecognized mod bits: "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>mod<span class="Delimiter">)</span> << <span class="cSpecial">'\n'</span><span class="Delimiter">;</span> +<span id="L40" class="LineNr"> 40 </span> <span class="Conceal">¦</span> exit<span class="Delimiter">(</span><span class="Constant">1</span><span class="Delimiter">);</span> +<span id="L41" class="LineNr"> 41 </span> <span class="Delimiter">}</span> +<span id="L42" class="LineNr"> 42 </span> <span class="Identifier">return</span> result<span class="Delimiter">;</span> +<span id="L43" class="LineNr"> 43 </span><span class="Delimiter">}</span> +<span id="L44" class="LineNr"> 44 </span> +<span id="L45" class="LineNr"> 45 </span><span class="SalientComment">//:: subtract</span> +<span id="L46" class="LineNr"> 46 </span> +<span id="L47" class="LineNr"> 47 </span><span class="Delimiter">:(scenario subtract_r32_from_r32)</span> +<span id="L48" class="LineNr"> 48 </span><span class="Special">% Reg[0].i = 10;</span> +<span id="L49" class="LineNr"> 49 </span><span class="Special">% Reg[3].i = 1;</span> +<span id="L50" class="LineNr"> 50 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L51" class="LineNr"> 51 </span> <span class="Constant">29</span> d8 <span class="Comment"># subtract EBX (reg 3) from EAX (reg 0)</span> +<span id="L52" class="LineNr"> 52 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L15'>reg</a> 3 from effective address</span> +<span id="L53" class="LineNr"> 53 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> +<span id="L54" class="LineNr"> 54 </span><span class="traceContains">+run: storing 0x00000009</span> +<span id="L55" class="LineNr"> 55 </span> +<span id="L56" class="LineNr"> 56 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L57" class="LineNr"> 57 </span><span class="Normal">case</span> <span class="Constant">0x29</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract r32 from r/m32</span> +<span id="L58" class="LineNr"> 58 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L59" class="LineNr"> 59 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L60" class="LineNr"> 60 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" from effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L61" class="LineNr"> 61 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L62" class="LineNr"> 62 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">);</span> +<span id="L63" class="LineNr"> 63 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L64" class="LineNr"> 64 </span><span class="Delimiter">}</span> +<span id="L65" class="LineNr"> 65 </span> +<span id="L66" class="LineNr"> 66 </span><span class="SalientComment">//:: and</span> +<span id="L67" class="LineNr"> 67 </span> +<span id="L68" class="LineNr"> 68 </span><span class="Delimiter">:(scenario and_r32_with_r32)</span> +<span id="L69" class="LineNr"> 69 </span><span class="Special">% Reg[0].i = 0x0a0b0c0d;</span> +<span id="L70" class="LineNr"> 70 </span><span class="Special">% Reg[3].i = 0x000000ff;</span> +<span id="L71" class="LineNr"> 71 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L72" class="LineNr"> 72 </span> <span class="Constant">21</span> d8 <span class="Comment"># and EBX (reg 3) with destination EAX (reg 0)</span> +<span id="L73" class="LineNr"> 73 </span><span class="traceContains">+run: and <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L74" class="LineNr"> 74 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> +<span id="L75" class="LineNr"> 75 </span><span class="traceContains">+run: storing 0x0000000d</span> +<span id="L76" class="LineNr"> 76 </span> +<span id="L77" class="LineNr"> 77 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L78" class="LineNr"> 78 </span><span class="Normal">case</span> <span class="Constant">0x21</span>: <span class="Delimiter">{</span> <span class="Comment">// and r32 with r/m32</span> +<span id="L79" class="LineNr"> 79 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L80" class="LineNr"> 80 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L81" class="LineNr"> 81 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"and <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" with effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L82" class="LineNr"> 82 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L83" class="LineNr"> 83 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>&<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">);</span> +<span id="L84" class="LineNr"> 84 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L85" class="LineNr"> 85 </span><span class="Delimiter">}</span> +<span id="L86" class="LineNr"> 86 </span> +<span id="L87" class="LineNr"> 87 </span><span class="SalientComment">//:: or</span> +<span id="L88" class="LineNr"> 88 </span> +<span id="L89" class="LineNr"> 89 </span><span class="Delimiter">:(scenario or_r32_with_r32)</span> +<span id="L90" class="LineNr"> 90 </span><span class="Special">% Reg[0].i = 0x0a0b0c0d;</span> +<span id="L91" class="LineNr"> 91 </span><span class="Special">% Reg[3].i = 0xa0b0c0d0;</span> +<span id="L92" class="LineNr"> 92 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L93" class="LineNr"> 93 </span> <span class="Error">09</span> d8 <span class="Comment"># or EBX (reg 3) with destination EAX (reg 0)</span> +<span id="L94" class="LineNr"> 94 </span><span class="traceContains">+run: or <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L95" class="LineNr"> 95 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> +<span id="L96" class="LineNr"> 96 </span><span class="traceContains">+run: storing 0xaabbccdd</span> +<span id="L97" class="LineNr"> 97 </span> +<span id="L98" class="LineNr"> 98 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L99" class="LineNr"> 99 </span><span class="Normal">case</span> <span class="Constant">0x09</span>: <span class="Delimiter">{</span> <span class="Comment">// or r32 with r/m32</span> +<span id="L100" class="LineNr">100 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L101" class="LineNr">101 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L102" class="LineNr">102 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"or <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" with effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L103" class="LineNr">103 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L104" class="LineNr">104 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>|<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">);</span> +<span id="L105" class="LineNr">105 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L106" class="LineNr">106 </span><span class="Delimiter">}</span> +<span id="L107" class="LineNr">107 </span> +<span id="L108" class="LineNr">108 </span><span class="SalientComment">//:: xor</span> +<span id="L109" class="LineNr">109 </span> +<span id="L110" class="LineNr">110 </span><span class="Delimiter">:(scenario xor_r32_with_r32)</span> +<span id="L111" class="LineNr">111 </span><span class="Special">% Reg[0].i = 0x0a0b0c0d;</span> +<span id="L112" class="LineNr">112 </span><span class="Special">% Reg[3].i = 0xaabbc0d0;</span> +<span id="L113" class="LineNr">113 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L114" class="LineNr">114 </span> <span class="Constant">31</span> d8 <span class="Comment"># xor EBX (reg 3) with destination EAX (reg 0)</span> +<span id="L115" class="LineNr">115 </span><span class="traceContains">+run: xor <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L116" class="LineNr">116 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 0</span> +<span id="L117" class="LineNr">117 </span><span class="traceContains">+run: storing 0xa0b0ccdd</span> +<span id="L118" class="LineNr">118 </span> +<span id="L119" class="LineNr">119 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L120" class="LineNr">120 </span><span class="Normal">case</span> <span class="Constant">0x31</span>: <span class="Delimiter">{</span> <span class="Comment">// xor r32 with r/m32</span> +<span id="L121" class="LineNr">121 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L122" class="LineNr">122 </span> <span class="Normal">uint8_t</span> arg2 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L123" class="LineNr">123 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"xor <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg2<span class="Delimiter">)</span> << <span class="Constant">" with effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L124" class="LineNr">124 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L125" class="LineNr">125 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>^<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> Reg[arg2]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">);</span> +<span id="L126" class="LineNr">126 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L127" class="LineNr">127 </span><span class="Delimiter">}</span> +<span id="L128" class="LineNr">128 </span> +<span id="L129" class="LineNr">129 </span><span class="SalientComment">//:: not</span> +<span id="L130" class="LineNr">130 </span> +<span id="L131" class="LineNr">131 </span><span class="Delimiter">:(scenario not_r32)</span> +<span id="L132" class="LineNr">132 </span><span class="Special">% Reg[3].i = 0x0f0f00ff;</span> +<span id="L133" class="LineNr">133 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L134" class="LineNr">134 </span> f7 c3 <span class="Comment"># not EBX (reg 3)</span> +<span id="L135" class="LineNr">135 </span><span class="traceContains">+run: 'not' of effective address</span> +<span id="L136" class="LineNr">136 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L137" class="LineNr">137 </span><span class="traceContains">+run: storing 0xf0f0ff00</span> +<span id="L138" class="LineNr">138 </span> +<span id="L139" class="LineNr">139 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L140" class="LineNr">140 </span><span class="Normal">case</span> <span class="Constant">0xf7</span>: <span class="Delimiter">{</span> <span class="Comment">// xor r32 with r/m32</span> +<span id="L141" class="LineNr">141 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L142" class="LineNr">142 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"'not' of effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L143" class="LineNr">143 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L144" class="LineNr">144 </span> *arg1 = ~<span class="Delimiter">(</span>*arg1<span class="Delimiter">);</span> +<span id="L145" class="LineNr">145 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"storing 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << *arg1 << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L146" class="LineNr">146 </span> SF = <span class="Delimiter">(</span>*arg1 >> <span class="Constant">31</span><span class="Delimiter">);</span> +<span id="L147" class="LineNr">147 </span> <a href='010core.cc.html#L30'>ZF</a> = <span class="Delimiter">(</span>*arg1 == <span class="Constant">0</span><span class="Delimiter">);</span> +<span id="L148" class="LineNr">148 </span> <a href='010core.cc.html#L31'>OF</a> = <span class="Constant">false</span><span class="Delimiter">;</span> +<span id="L149" class="LineNr">149 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L150" class="LineNr">150 </span><span class="Delimiter">}</span> </pre> </body> </html> diff --git a/html/subx/012indirect_addressing.cc.html b/html/subx/012indirect_addressing.cc.html index 8f90ff92..8f0f7adf 100644 --- a/html/subx/012indirect_addressing.cc.html +++ b/html/subx/012indirect_addressing.cc.html @@ -26,6 +26,7 @@ a:hover { text-decoration: underline; } .Identifier { color: #c0a020; } .Normal { color: #aaaaaa; background-color: #080808; padding-bottom: 1px; } .PreProc { color: #800080; } +.Error { color: #ffffff; background-color: #ff6060; padding-bottom: 1px; } .traceContains { color: #008000; } --> </style> @@ -61,87 +62,219 @@ if ('onhashchange' in window) { </head> <body onload='JumpToLine();'> <pre id='vimCodeElement'> -<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: operating on memory at the address provided by some register</span> -<span id="L2" class="LineNr"> 2 </span> -<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_r32_to_mem_at_r32)</span> -<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[3].i = 0x10;</span> -<span id="L5" class="LineNr"> 5 </span><span class="Special">% Reg[0].i = 0x60;</span> -<span id="L6" class="LineNr"> 6 </span><span class="Comment"># word in addresses 0x60-0x63 has value 1</span> -<span id="L7" class="LineNr"> 7 </span><span class="Special">% Mem.at(0x60) = 1;</span> -<span id="L8" class="LineNr"> 8 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L9" class="LineNr"> 9 </span> <span class="PreProc">0</span><span class="Constant">1</span> <span class="Constant">18</span> <span class="Comment"># add EBX (reg 3) to *EAX (reg 0)</span> -<span id="L10" class="LineNr">10 </span><span class="traceContains">+run: add <a href='010core.cc.html#L15'>reg</a> 3 to effective address</span> -<span id="L11" class="LineNr">11 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> -<span id="L12" class="LineNr">12 </span><span class="traceContains">+run: storing 0x00000011</span> -<span id="L13" class="LineNr">13 </span> -<span id="L14" class="LineNr">14 </span><span class="Delimiter">:(before "End Mod Special-cases")</span> -<span id="L15" class="LineNr">15 </span><span class="Normal">case</span> <span class="Constant">0</span>: -<span id="L16" class="LineNr">16 </span> <span class="Comment">// mod 0 is usually indirect addressing</span> -<span id="L17" class="LineNr">17 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>rm<span class="Delimiter">)</span> <span class="Delimiter">{</span> -<span id="L18" class="LineNr">18 </span> <span class="Normal">default</span>: -<span id="L19" class="LineNr">19 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"effective address is mem at address 0x"</span> << std::hex << Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a> << <span class="Constant">" (reg "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>rm<span class="Delimiter">)</span> << <span class="Constant">")"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L20" class="LineNr">20 </span> <span class="Conceal">¦</span> assert<span class="Delimiter">(</span>Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a> + <span class="Normal">sizeof</span><span class="Delimiter">(</span><span class="Normal">int32_t</span><span class="Delimiter">)</span> <= <a href='010core.cc.html#L61'>Mem</a><span class="Delimiter">.</span>size<span class="Delimiter">());</span> -<span id="L21" class="LineNr">21 </span> <span class="Conceal">¦</span> result = <span class="Normal">reinterpret_cast</span><<span class="Normal">int32_t</span>*><span class="Delimiter">(</span>&Mem<span class="Delimiter">.</span>at<span class="Delimiter">(</span>Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">));</span> <span class="Comment">// rely on the host itself being in little-endian order</span> -<span id="L22" class="LineNr">22 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L23" class="LineNr">23 </span> <span class="Comment">// End Mod 0 Special-cases</span> -<span id="L24" class="LineNr">24 </span> <span class="Delimiter">}</span> -<span id="L25" class="LineNr">25 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L26" class="LineNr">26 </span> -<span id="L27" class="LineNr">27 </span><span class="Comment">//:</span> -<span id="L28" class="LineNr">28 </span> -<span id="L29" class="LineNr">29 </span><span class="Delimiter">:(scenario add_mem_at_r32_to_r32)</span> -<span id="L30" class="LineNr">30 </span><span class="Special">% Reg[0].i = 0x60;</span> -<span id="L31" class="LineNr">31 </span><span class="Special">% Reg[3].i = 0x10;</span> -<span id="L32" class="LineNr">32 </span><span class="Special">% Mem.at(0x60) = 1;</span> -<span id="L33" class="LineNr">33 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L34" class="LineNr">34 </span> <span class="PreProc">0</span><span class="Constant">3</span> <span class="Constant">18</span> <span class="Comment"># add *EAX (reg 0) to EBX (reg 3)</span> -<span id="L35" class="LineNr">35 </span><span class="traceContains">+run: add effective address to <a href='010core.cc.html#L15'>reg</a> 3</span> -<span id="L36" class="LineNr">36 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> -<span id="L37" class="LineNr">37 </span><span class="traceContains">+run: storing 0x00000011</span> -<span id="L38" class="LineNr">38 </span> -<span id="L39" class="LineNr">39 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L40" class="LineNr">40 </span><span class="Normal">case</span> <span class="Constant">0x03</span>: <span class="Delimiter">{</span> <span class="Comment">// add r/m32 to r32</span> -<span id="L41" class="LineNr">41 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> -<span id="L42" class="LineNr">42 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> -<span id="L43" class="LineNr">43 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"add effective address to <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L44" class="LineNr">44 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> -<span id="L45" class="LineNr">45 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> -<span id="L46" class="LineNr">46 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L47" class="LineNr">47 </span><span class="Delimiter">}</span> -<span id="L48" class="LineNr">48 </span> -<span id="L49" class="LineNr">49 </span><span class="SalientComment">//:: subtract</span> -<span id="L50" class="LineNr">50 </span> -<span id="L51" class="LineNr">51 </span><span class="Delimiter">:(scenario subtract_r32_from_mem_at_r32)</span> -<span id="L52" class="LineNr">52 </span><span class="Special">% Reg[0].i = 0x60;</span> -<span id="L53" class="LineNr">53 </span><span class="Special">% Mem.at(0x60) = 10;</span> -<span id="L54" class="LineNr">54 </span><span class="Special">% Reg[3].i = 1;</span> -<span id="L55" class="LineNr">55 </span><span class="Comment"># op ModRM SIB displacement immediate</span> -<span id="L56" class="LineNr">56 </span> <span class="Constant">29</span> <span class="Constant">18</span> <span class="Comment"># subtract EBX (reg 3) from *EAX (reg 0)</span> -<span id="L57" class="LineNr">57 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L15'>reg</a> 3 from effective address</span> -<span id="L58" class="LineNr">58 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> -<span id="L59" class="LineNr">59 </span><span class="traceContains">+run: storing 0x00000009</span> -<span id="L60" class="LineNr">60 </span> -<span id="L61" class="LineNr">61 </span><span class="Comment">//:</span> -<span id="L62" class="LineNr">62 </span> -<span id="L63" class="LineNr">63 </span><span class="Delimiter">:(scenario subtract_mem_at_r32_from_r32)</span> -<span id="L64" class="LineNr">64 </span><span class="Special">% Reg[0].i = 0x60;</span> -<span id="L65" class="LineNr">65 </span><span class="Special">% Mem.at(0x60) = 1;</span> -<span id="L66" class="LineNr">66 </span><span class="Special">% Reg[3].i = 10;</span> -<span id="L67" class="LineNr">67 </span><span class="Comment"># op ModRM SIB displacement immediate</span> -<span id="L68" class="LineNr">68 </span> 2b <span class="Constant">18</span> <span class="Comment"># subtract *EAX (reg 0) from EBX (reg 3)</span> -<span id="L69" class="LineNr">69 </span><span class="traceContains">+run: subtract effective address from <a href='010core.cc.html#L15'>reg</a> 3</span> -<span id="L70" class="LineNr">70 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> -<span id="L71" class="LineNr">71 </span><span class="traceContains">+run: storing 0x00000009</span> -<span id="L72" class="LineNr">72 </span> -<span id="L73" class="LineNr">73 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L74" class="LineNr">74 </span><span class="Normal">case</span> <span class="Constant">0x2b</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract r/m32 from r32</span> -<span id="L75" class="LineNr">75 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> -<span id="L76" class="LineNr">76 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> -<span id="L77" class="LineNr">77 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract effective address from <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L78" class="LineNr">78 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> -<span id="L79" class="LineNr">79 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> -<span id="L80" class="LineNr">80 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L81" class="LineNr">81 </span><span class="Delimiter">}</span> +<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: operating on memory at the address provided by some register</span> +<span id="L2" class="LineNr"> 2 </span> +<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_r32_to_mem_at_r32)</span> +<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[3].i = 0x10;</span> +<span id="L5" class="LineNr"> 5 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L6" class="LineNr"> 6 </span><span class="Comment"># word in addresses 0x60-0x63 has value 1</span> +<span id="L7" class="LineNr"> 7 </span><span class="Special">% Mem.at(0x60) = 1;</span> +<span id="L8" class="LineNr"> 8 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L9" class="LineNr"> 9 </span> <span class="PreProc">0</span><span class="Constant">1</span> <span class="Constant">18</span> <span class="Comment"># add EBX (reg 3) to *EAX (reg 0)</span> +<span id="L10" class="LineNr"> 10 </span><span class="traceContains">+run: add <a href='010core.cc.html#L15'>reg</a> 3 to effective address</span> +<span id="L11" class="LineNr"> 11 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L12" class="LineNr"> 12 </span><span class="traceContains">+run: storing 0x00000011</span> +<span id="L13" class="LineNr"> 13 </span> +<span id="L14" class="LineNr"> 14 </span><span class="Delimiter">:(before "End Mod Special-cases")</span> +<span id="L15" class="LineNr"> 15 </span><span class="Normal">case</span> <span class="Constant">0</span>: +<span id="L16" class="LineNr"> 16 </span> <span class="Comment">// mod 0 is usually indirect addressing</span> +<span id="L17" class="LineNr"> 17 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>rm<span class="Delimiter">)</span> <span class="Delimiter">{</span> +<span id="L18" class="LineNr"> 18 </span> <span class="Normal">default</span>: +<span id="L19" class="LineNr"> 19 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"effective address is mem at address 0x"</span> << std::hex << Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a> << <span class="Constant">" (reg "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>rm<span class="Delimiter">)</span> << <span class="Constant">")"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L20" class="LineNr"> 20 </span> <span class="Conceal">¦</span> assert<span class="Delimiter">(</span>Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a> + <span class="Normal">sizeof</span><span class="Delimiter">(</span><span class="Normal">int32_t</span><span class="Delimiter">)</span> <= <a href='010core.cc.html#L61'>Mem</a><span class="Delimiter">.</span>size<span class="Delimiter">());</span> +<span id="L21" class="LineNr"> 21 </span> <span class="Conceal">¦</span> result = <span class="Normal">reinterpret_cast</span><<span class="Normal">int32_t</span>*><span class="Delimiter">(</span>&Mem<span class="Delimiter">.</span>at<span class="Delimiter">(</span>Reg[rm]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">));</span> <span class="Comment">// rely on the host itself being in little-endian order</span> +<span id="L22" class="LineNr"> 22 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L23" class="LineNr"> 23 </span> <span class="Comment">// End Mod 0 Special-cases</span> +<span id="L24" class="LineNr"> 24 </span> <span class="Delimiter">}</span> +<span id="L25" class="LineNr"> 25 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L26" class="LineNr"> 26 </span> +<span id="L27" class="LineNr"> 27 </span><span class="Comment">//:</span> +<span id="L28" class="LineNr"> 28 </span> +<span id="L29" class="LineNr"> 29 </span><span class="Delimiter">:(scenario add_mem_at_r32_to_r32)</span> +<span id="L30" class="LineNr"> 30 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L31" class="LineNr"> 31 </span><span class="Special">% Reg[3].i = 0x10;</span> +<span id="L32" class="LineNr"> 32 </span><span class="Special">% Mem.at(0x60) = 1;</span> +<span id="L33" class="LineNr"> 33 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L34" class="LineNr"> 34 </span> <span class="PreProc">0</span><span class="Constant">3</span> <span class="Constant">18</span> <span class="Comment"># add *EAX (reg 0) to EBX (reg 3)</span> +<span id="L35" class="LineNr"> 35 </span><span class="traceContains">+run: add effective address to <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L36" class="LineNr"> 36 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L37" class="LineNr"> 37 </span><span class="traceContains">+run: storing 0x00000011</span> +<span id="L38" class="LineNr"> 38 </span> +<span id="L39" class="LineNr"> 39 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L40" class="LineNr"> 40 </span><span class="Normal">case</span> <span class="Constant">0x03</span>: <span class="Delimiter">{</span> <span class="Comment">// add r/m32 to r32</span> +<span id="L41" class="LineNr"> 41 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L42" class="LineNr"> 42 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L43" class="LineNr"> 43 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"add effective address to <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L44" class="LineNr"> 44 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L45" class="LineNr"> 45 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> +<span id="L46" class="LineNr"> 46 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L47" class="LineNr"> 47 </span><span class="Delimiter">}</span> +<span id="L48" class="LineNr"> 48 </span> +<span id="L49" class="LineNr"> 49 </span><span class="SalientComment">//:: subtract</span> +<span id="L50" class="LineNr"> 50 </span> +<span id="L51" class="LineNr"> 51 </span><span class="Delimiter">:(scenario subtract_r32_from_mem_at_r32)</span> +<span id="L52" class="LineNr"> 52 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L53" class="LineNr"> 53 </span><span class="Special">% Mem.at(0x60) = 10;</span> +<span id="L54" class="LineNr"> 54 </span><span class="Special">% Reg[3].i = 1;</span> +<span id="L55" class="LineNr"> 55 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L56" class="LineNr"> 56 </span> <span class="Constant">29</span> <span class="Constant">18</span> <span class="Comment"># subtract EBX (reg 3) from *EAX (reg 0)</span> +<span id="L57" class="LineNr"> 57 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L15'>reg</a> 3 from effective address</span> +<span id="L58" class="LineNr"> 58 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L59" class="LineNr"> 59 </span><span class="traceContains">+run: storing 0x00000009</span> +<span id="L60" class="LineNr"> 60 </span> +<span id="L61" class="LineNr"> 61 </span><span class="Comment">//:</span> +<span id="L62" class="LineNr"> 62 </span> +<span id="L63" class="LineNr"> 63 </span><span class="Delimiter">:(scenario subtract_mem_at_r32_from_r32)</span> +<span id="L64" class="LineNr"> 64 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L65" class="LineNr"> 65 </span><span class="Special">% Mem.at(0x60) = 1;</span> +<span id="L66" class="LineNr"> 66 </span><span class="Special">% Reg[3].i = 10;</span> +<span id="L67" class="LineNr"> 67 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L68" class="LineNr"> 68 </span> 2b <span class="Constant">18</span> <span class="Comment"># subtract *EAX (reg 0) from EBX (reg 3)</span> +<span id="L69" class="LineNr"> 69 </span><span class="traceContains">+run: subtract effective address from <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L70" class="LineNr"> 70 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L71" class="LineNr"> 71 </span><span class="traceContains">+run: storing 0x00000009</span> +<span id="L72" class="LineNr"> 72 </span> +<span id="L73" class="LineNr"> 73 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L74" class="LineNr"> 74 </span><span class="Normal">case</span> <span class="Constant">0x2b</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract r/m32 from r32</span> +<span id="L75" class="LineNr"> 75 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L76" class="LineNr"> 76 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L77" class="LineNr"> 77 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract effective address from <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L78" class="LineNr"> 78 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L79" class="LineNr"> 79 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> +<span id="L80" class="LineNr"> 80 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L81" class="LineNr"> 81 </span><span class="Delimiter">}</span> +<span id="L82" class="LineNr"> 82 </span> +<span id="L83" class="LineNr"> 83 </span><span class="SalientComment">//:: and</span> +<span id="L84" class="LineNr"> 84 </span> +<span id="L85" class="LineNr"> 85 </span><span class="Delimiter">:(scenario and_r32_with_mem_at_r32)</span> +<span id="L86" class="LineNr"> 86 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L87" class="LineNr"> 87 </span><span class="Special">% Mem.at(0x60) = 0x0d;</span> +<span id="L88" class="LineNr"> 88 </span><span class="Special">% Mem.at(0x61) = 0x0c;</span> +<span id="L89" class="LineNr"> 89 </span><span class="Special">% Mem.at(0x62) = 0x0b;</span> +<span id="L90" class="LineNr"> 90 </span><span class="Special">% Mem.at(0x63) = 0x0a;</span> +<span id="L91" class="LineNr"> 91 </span><span class="Special">% Reg[3].i = 0xff;</span> +<span id="L92" class="LineNr"> 92 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L93" class="LineNr"> 93 </span> <span class="Constant">21</span> <span class="Constant">18</span> <span class="Comment"># and EBX (reg 3) with *EAX (reg 0)</span> +<span id="L94" class="LineNr"> 94 </span><span class="traceContains">+run: and <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L95" class="LineNr"> 95 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L96" class="LineNr"> 96 </span><span class="traceContains">+run: storing 0x0000000d</span> +<span id="L97" class="LineNr"> 97 </span> +<span id="L98" class="LineNr"> 98 </span><span class="Comment">//:</span> +<span id="L99" class="LineNr"> 99 </span> +<span id="L100" class="LineNr">100 </span><span class="Delimiter">:(scenario and_mem_at_r32_with_r32)</span> +<span id="L101" class="LineNr">101 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L102" class="LineNr">102 </span><span class="Special">% Mem.at(0x60) = 0xff;</span> +<span id="L103" class="LineNr">103 </span><span class="Special">% Reg[3].i = 0x0a0b0c0d;</span> +<span id="L104" class="LineNr">104 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L105" class="LineNr">105 </span> <span class="Constant">23</span> <span class="Constant">18</span> <span class="Comment"># and *EAX (reg 0) with EBX (reg 3)</span> +<span id="L106" class="LineNr">106 </span><span class="traceContains">+run: and effective address with <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L107" class="LineNr">107 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L108" class="LineNr">108 </span><span class="traceContains">+run: storing 0x0000000d</span> +<span id="L109" class="LineNr">109 </span> +<span id="L110" class="LineNr">110 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L111" class="LineNr">111 </span><span class="Normal">case</span> <span class="Constant">0x23</span>: <span class="Delimiter">{</span> <span class="Comment">// and r/m32 with r32</span> +<span id="L112" class="LineNr">112 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L113" class="LineNr">113 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L114" class="LineNr">114 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"and effective address with <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L115" class="LineNr">115 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L116" class="LineNr">116 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>&<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> +<span id="L117" class="LineNr">117 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L118" class="LineNr">118 </span><span class="Delimiter">}</span> +<span id="L119" class="LineNr">119 </span> +<span id="L120" class="LineNr">120 </span><span class="SalientComment">//:: or</span> +<span id="L121" class="LineNr">121 </span> +<span id="L122" class="LineNr">122 </span><span class="Delimiter">:(scenario or_r32_with_mem_at_r32)</span> +<span id="L123" class="LineNr">123 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L124" class="LineNr">124 </span><span class="Special">% Mem.at(0x60) = 0x0d;</span> +<span id="L125" class="LineNr">125 </span><span class="Special">% Mem.at(0x61) = 0x0c;</span> +<span id="L126" class="LineNr">126 </span><span class="Special">% Mem.at(0x62) = 0x0b;</span> +<span id="L127" class="LineNr">127 </span><span class="Special">% Mem.at(0x63) = 0x0a;</span> +<span id="L128" class="LineNr">128 </span><span class="Special">% Reg[3].i = 0xa0b0c0d0;</span> +<span id="L129" class="LineNr">129 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L130" class="LineNr">130 </span> <span class="Error">09</span> <span class="Constant">18</span> <span class="Comment"># or EBX (reg 3) with *EAX (reg 0)</span> +<span id="L131" class="LineNr">131 </span><span class="traceContains">+run: or <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L132" class="LineNr">132 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L133" class="LineNr">133 </span><span class="traceContains">+run: storing 0xaabbccdd</span> +<span id="L134" class="LineNr">134 </span> +<span id="L135" class="LineNr">135 </span><span class="Comment">//:</span> +<span id="L136" class="LineNr">136 </span> +<span id="L137" class="LineNr">137 </span><span class="Delimiter">:(scenario or_mem_at_r32_with_r32)</span> +<span id="L138" class="LineNr">138 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L139" class="LineNr">139 </span><span class="Special">% Mem.at(0x60) = 0x0d;</span> +<span id="L140" class="LineNr">140 </span><span class="Special">% Mem.at(0x61) = 0x0c;</span> +<span id="L141" class="LineNr">141 </span><span class="Special">% Mem.at(0x62) = 0x0b;</span> +<span id="L142" class="LineNr">142 </span><span class="Special">% Mem.at(0x63) = 0x0a;</span> +<span id="L143" class="LineNr">143 </span><span class="Special">% Reg[3].i = 0xa0b0c0d0;</span> +<span id="L144" class="LineNr">144 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L145" class="LineNr">145 </span> 0b <span class="Constant">18</span> <span class="Comment"># or *EAX (reg 0) with EBX (reg 3)</span> +<span id="L146" class="LineNr">146 </span><span class="traceContains">+run: or effective address with <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L147" class="LineNr">147 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L148" class="LineNr">148 </span><span class="traceContains">+run: storing 0xaabbccdd</span> +<span id="L149" class="LineNr">149 </span> +<span id="L150" class="LineNr">150 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L151" class="LineNr">151 </span><span class="Normal">case</span> <span class="Constant">0x0b</span>: <span class="Delimiter">{</span> <span class="Comment">// or r/m32 with r32</span> +<span id="L152" class="LineNr">152 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L153" class="LineNr">153 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L154" class="LineNr">154 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"or effective address with <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L155" class="LineNr">155 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L156" class="LineNr">156 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>|<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> +<span id="L157" class="LineNr">157 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L158" class="LineNr">158 </span><span class="Delimiter">}</span> +<span id="L159" class="LineNr">159 </span> +<span id="L160" class="LineNr">160 </span><span class="SalientComment">//:: xor</span> +<span id="L161" class="LineNr">161 </span> +<span id="L162" class="LineNr">162 </span><span class="Delimiter">:(scenario xor_r32_with_mem_at_r32)</span> +<span id="L163" class="LineNr">163 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L164" class="LineNr">164 </span><span class="Special">% Mem.at(0x60) = 0x0d;</span> +<span id="L165" class="LineNr">165 </span><span class="Special">% Mem.at(0x61) = 0x0c;</span> +<span id="L166" class="LineNr">166 </span><span class="Special">% Mem.at(0x62) = 0xbb;</span> +<span id="L167" class="LineNr">167 </span><span class="Special">% Mem.at(0x63) = 0xaa;</span> +<span id="L168" class="LineNr">168 </span><span class="Special">% Reg[3].i = 0xa0b0c0d0;</span> +<span id="L169" class="LineNr">169 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L170" class="LineNr">170 </span> <span class="Constant">31</span> <span class="Constant">18</span> <span class="Comment"># xor EBX (reg 3) with *EAX (reg 0)</span> +<span id="L171" class="LineNr">171 </span><span class="traceContains">+run: xor <a href='010core.cc.html#L15'>reg</a> 3 with effective address</span> +<span id="L172" class="LineNr">172 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L173" class="LineNr">173 </span><span class="traceContains">+run: storing 0x0a0bccdd</span> +<span id="L174" class="LineNr">174 </span> +<span id="L175" class="LineNr">175 </span><span class="Comment">//:</span> +<span id="L176" class="LineNr">176 </span> +<span id="L177" class="LineNr">177 </span><span class="Delimiter">:(scenario xor_mem_at_r32_with_r32)</span> +<span id="L178" class="LineNr">178 </span><span class="Special">% Reg[0].i = 0x60;</span> +<span id="L179" class="LineNr">179 </span><span class="Special">% Mem.at(0x60) = 0x0d;</span> +<span id="L180" class="LineNr">180 </span><span class="Special">% Mem.at(0x61) = 0x0c;</span> +<span id="L181" class="LineNr">181 </span><span class="Special">% Mem.at(0x62) = 0x0b;</span> +<span id="L182" class="LineNr">182 </span><span class="Special">% Mem.at(0x63) = 0x0a;</span> +<span id="L183" class="LineNr">183 </span><span class="Special">% Reg[3].i = 0xa0b0c0d0;</span> +<span id="L184" class="LineNr">184 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L185" class="LineNr">185 </span> <span class="Constant">33</span> <span class="Constant">18</span> <span class="Comment"># xor *EAX (reg 0) with EBX (reg 3)</span> +<span id="L186" class="LineNr">186 </span><span class="traceContains">+run: xor effective address with <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L187" class="LineNr">187 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 0)</span> +<span id="L188" class="LineNr">188 </span><span class="traceContains">+run: storing 0xaabbccdd</span> +<span id="L189" class="LineNr">189 </span> +<span id="L190" class="LineNr">190 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L191" class="LineNr">191 </span><span class="Normal">case</span> <span class="Constant">0x33</span>: <span class="Delimiter">{</span> <span class="Comment">// xor r/m32 with r32</span> +<span id="L192" class="LineNr">192 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L193" class="LineNr">193 </span> <span class="Normal">uint8_t</span> arg1 = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> +<span id="L194" class="LineNr">194 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"xor effective address with <a href='010core.cc.html#L15'>reg</a> "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>arg1<span class="Delimiter">)</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L195" class="LineNr">195 </span> <span class="Normal">const</span> <span class="Normal">int32_t</span>* arg2 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L196" class="LineNr">196 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>|<span class="Delimiter">,</span> Reg[arg1]<span class="Delimiter">.</span><a href='010core.cc.html#L17'>u</a><span class="Delimiter">,</span> *arg2<span class="Delimiter">);</span> +<span id="L197" class="LineNr">197 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L198" class="LineNr">198 </span><span class="Delimiter">}</span> +<span id="L199" class="LineNr">199 </span> +<span id="L200" class="LineNr">200 </span><span class="SalientComment">//:: not</span> +<span id="L201" class="LineNr">201 </span> +<span id="L202" class="LineNr">202 </span><span class="Delimiter">:(scenario not_r32_with_mem_at_r32)</span> +<span id="L203" class="LineNr">203 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L204" class="LineNr">204 </span><span class="Comment"># word at 0x60 is 0x0f0f00ff</span> +<span id="L205" class="LineNr">205 </span><span class="Special">% Mem.at(0x60) = 0xff;</span> +<span id="L206" class="LineNr">206 </span><span class="Special">% Mem.at(0x61) = 0x00;</span> +<span id="L207" class="LineNr">207 </span><span class="Special">% Mem.at(0x62) = 0x0f;</span> +<span id="L208" class="LineNr">208 </span><span class="Special">% Mem.at(0x63) = 0x0f;</span> +<span id="L209" class="LineNr">209 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L210" class="LineNr">210 </span> f7 <span class="PreProc">0</span><span class="Constant">3</span> <span class="Comment"># negate *EBX (reg 3)</span> +<span id="L211" class="LineNr">211 </span><span class="traceContains">+run: 'not' of effective address</span> +<span id="L212" class="LineNr">212 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L213" class="LineNr">213 </span><span class="traceContains">+run: storing 0xf0f0ff00</span> </pre> </body> </html> diff --git a/html/subx/013immediate_addressing.cc.html b/html/subx/013immediate_addressing.cc.html index 3cb55938..b8ee4442 100644 --- a/html/subx/013immediate_addressing.cc.html +++ b/html/subx/013immediate_addressing.cc.html @@ -62,95 +62,242 @@ if ('onhashchange' in window) { </head> <body onload='JumpToLine();'> <pre id='vimCodeElement'> -<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: instructions that (immediately) contain an argument to act with</span> -<span id="L2" class="LineNr"> 2 </span> -<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_imm32_to_r32)</span> -<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[3].i = 1;</span> -<span id="L5" class="LineNr"> 5 </span><span class="Comment"># op ModRM SIB displacement immediate</span> -<span id="L6" class="LineNr"> 6 </span> <span class="Constant">81</span> c3 0a 0b 0c 0d <span class="Comment"># add 0x0d0c0b0a to EBX (reg 3)</span> -<span id="L7" class="LineNr"> 7 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> -<span id="L8" class="LineNr"> 8 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> -<span id="L9" class="LineNr"> 9 </span><span class="traceContains">+run: subop add</span> -<span id="L10" class="LineNr">10 </span><span class="traceContains">+run: storing 0x0d0c0b0b</span> -<span id="L11" class="LineNr">11 </span> -<span id="L12" class="LineNr">12 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L13" class="LineNr">13 </span><span class="Normal">case</span> <span class="Constant">0x81</span>: <span class="Delimiter">{</span> <span class="Comment">// combine imm32 with r/m32</span> -<span id="L14" class="LineNr">14 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> -<span id="L15" class="LineNr">15 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> -<span id="L16" class="LineNr">16 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"combine <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" with effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L17" class="LineNr">17 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> -<span id="L18" class="LineNr">18 </span> <span class="Normal">uint8_t</span> subop = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> <span class="Comment">// middle 3 'reg opcode' bits</span> -<span id="L19" class="LineNr">19 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>subop<span class="Delimiter">)</span> <span class="Delimiter">{</span> -<span id="L20" class="LineNr">20 </span> <span class="Normal">case</span> <span class="Constant">0</span>: -<span id="L21" class="LineNr">21 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop add"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L22" class="LineNr">22 </span> <span class="Conceal">¦</span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> -<span id="L23" class="LineNr">23 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L24" class="LineNr">24 </span> <span class="Comment">// End Op 81 Subops</span> -<span id="L25" class="LineNr">25 </span> <span class="Normal">default</span>: -<span id="L26" class="LineNr">26 </span> <span class="Conceal">¦</span> cerr << <span class="Constant">"unrecognized sub-opcode after 81: "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>subop<span class="Delimiter">)</span> << <span class="cSpecial">'\n'</span><span class="Delimiter">;</span> -<span id="L27" class="LineNr">27 </span> <span class="Conceal">¦</span> exit<span class="Delimiter">(</span><span class="Constant">1</span><span class="Delimiter">);</span> -<span id="L28" class="LineNr">28 </span> <span class="Delimiter">}</span> -<span id="L29" class="LineNr">29 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L30" class="LineNr">30 </span><span class="Delimiter">}</span> -<span id="L31" class="LineNr">31 </span> -<span id="L32" class="LineNr">32 </span><span class="Comment">//:</span> -<span id="L33" class="LineNr">33 </span> -<span id="L34" class="LineNr">34 </span><span class="Delimiter">:(scenario add_imm32_to_mem_at_r32)</span> -<span id="L35" class="LineNr">35 </span><span class="Special">% Reg[3].i = 0x60;</span> -<span id="L36" class="LineNr">36 </span><span class="Special">% Mem.at(0x60) = 1;</span> -<span id="L37" class="LineNr">37 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L38" class="LineNr">38 </span> <span class="Constant">81</span> <span class="PreProc">0</span><span class="Constant">3</span> 0a 0b 0c 0d <span class="Comment"># add 0x0d0c0b0a to *EBX (reg 3)</span> -<span id="L39" class="LineNr">39 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> -<span id="L40" class="LineNr">40 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> -<span id="L41" class="LineNr">41 </span><span class="traceContains">+run: subop add</span> -<span id="L42" class="LineNr">42 </span><span class="traceContains">+run: storing 0x0d0c0b0b</span> -<span id="L43" class="LineNr">43 </span> -<span id="L44" class="LineNr">44 </span><span class="SalientComment">//:: subtract</span> -<span id="L45" class="LineNr">45 </span> -<span id="L46" class="LineNr">46 </span><span class="Delimiter">:(scenario subtract_imm32_from_eax)</span> -<span id="L47" class="LineNr">47 </span><span class="Special">% Reg[EAX].i = 0x0d0c0baa;</span> -<span id="L48" class="LineNr">48 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> -<span id="L49" class="LineNr">49 </span> 2d 0a 0b 0c 0d <span class="Comment"># subtract 0x0d0c0b0a from EAX (reg 0)</span> -<span id="L50" class="LineNr">50 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a from <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a></span> -<span id="L51" class="LineNr">51 </span><span class="traceContains">+run: storing 0x000000a0</span> -<span id="L52" class="LineNr">52 </span> -<span id="L53" class="LineNr">53 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> -<span id="L54" class="LineNr">54 </span><span class="Normal">case</span> <span class="Constant">0x2d</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract imm32 from EAX</span> -<span id="L55" class="LineNr">55 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> -<span id="L56" class="LineNr">56 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" from <a href='010core.cc.html#L15'>reg</a> EAX"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L57" class="LineNr">57 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> -<span id="L58" class="LineNr">58 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L59" class="LineNr">59 </span><span class="Delimiter">}</span> -<span id="L60" class="LineNr">60 </span> -<span id="L61" class="LineNr">61 </span><span class="Comment">//:</span> -<span id="L62" class="LineNr">62 </span> -<span id="L63" class="LineNr">63 </span><span class="Delimiter">:(scenario subtract_imm32_from_mem_at_r32)</span> -<span id="L64" class="LineNr">64 </span><span class="Special">% Reg[3].i = 0x60;</span> -<span id="L65" class="LineNr">65 </span><span class="Special">% Mem.at(0x60) = 10;</span> -<span id="L66" class="LineNr">66 </span><span class="Comment"># op ModRM SIB displacement immediate</span> -<span id="L67" class="LineNr">67 </span> <span class="Constant">81</span> 2b <span class="PreProc">0</span><span class="Constant">1</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="Comment"># subtract 1 from *EBX (reg 3)</span> -<span id="L68" class="LineNr">68 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x00000001 with effective address</span> -<span id="L69" class="LineNr">69 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> -<span id="L70" class="LineNr">70 </span><span class="traceContains">+run: subop subtract</span> -<span id="L71" class="LineNr">71 </span><span class="traceContains">+run: storing 0x00000009</span> -<span id="L72" class="LineNr">72 </span> -<span id="L73" class="LineNr">73 </span><span class="Comment">//:</span> -<span id="L74" class="LineNr">74 </span> -<span id="L75" class="LineNr">75 </span><span class="Delimiter">:(scenario subtract_imm32_from_r32)</span> -<span id="L76" class="LineNr">76 </span><span class="Special">% Reg[3].i = 10;</span> -<span id="L77" class="LineNr">77 </span><span class="Comment"># op ModRM SIB displacement immediate</span> -<span id="L78" class="LineNr">78 </span> <span class="Constant">81</span> eb <span class="PreProc">0</span><span class="Constant">1</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="Comment"># subtract 1 from EBX (reg 3)</span> -<span id="L79" class="LineNr">79 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x00000001 with effective address</span> -<span id="L80" class="LineNr">80 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> -<span id="L81" class="LineNr">81 </span><span class="traceContains">+run: subop subtract</span> -<span id="L82" class="LineNr">82 </span><span class="traceContains">+run: storing 0x00000009</span> -<span id="L83" class="LineNr">83 </span> -<span id="L84" class="LineNr">84 </span><span class="Delimiter">:(before "End Op 81 Subops")</span> -<span id="L85" class="LineNr">85 </span><span class="Normal">case</span> <span class="Constant">5</span>: <span class="Delimiter">{</span> -<span id="L86" class="LineNr">86 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop subtract"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> -<span id="L87" class="LineNr">87 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> -<span id="L88" class="LineNr">88 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> -<span id="L89" class="LineNr">89 </span><span class="Delimiter">}</span> +<span id="L1" class="LineNr"> 1 </span><span class="Comment">//: instructions that (immediately) contain an argument to act with</span> +<span id="L2" class="LineNr"> 2 </span> +<span id="L3" class="LineNr"> 3 </span><span class="Delimiter">:(scenario add_imm32_to_r32)</span> +<span id="L4" class="LineNr"> 4 </span><span class="Special">% Reg[3].i = 1;</span> +<span id="L5" class="LineNr"> 5 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L6" class="LineNr"> 6 </span> <span class="Constant">81</span> c3 0a 0b 0c 0d <span class="Comment"># add 0x0d0c0b0a to EBX (reg 3)</span> +<span id="L7" class="LineNr"> 7 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L8" class="LineNr"> 8 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L9" class="LineNr"> 9 </span><span class="traceContains">+run: subop add</span> +<span id="L10" class="LineNr"> 10 </span><span class="traceContains">+run: storing 0x0d0c0b0b</span> +<span id="L11" class="LineNr"> 11 </span> +<span id="L12" class="LineNr"> 12 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L13" class="LineNr"> 13 </span><span class="Normal">case</span> <span class="Constant">0x81</span>: <span class="Delimiter">{</span> <span class="Comment">// combine imm32 with r/m32</span> +<span id="L14" class="LineNr"> 14 </span> <span class="Normal">uint8_t</span> modrm = <a href='010core.cc.html#L202'>next</a><span class="Delimiter">();</span> +<span id="L15" class="LineNr"> 15 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> +<span id="L16" class="LineNr"> 16 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"combine <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" with effective address"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L17" class="LineNr"> 17 </span> <span class="Normal">int32_t</span>* arg1 = <a href='011direct_addressing.cc.html#L26'>effective_address</a><span class="Delimiter">(</span>modrm<span class="Delimiter">);</span> +<span id="L18" class="LineNr"> 18 </span> <span class="Normal">uint8_t</span> subop = <span class="Delimiter">(</span>modrm>><span class="Constant">3</span><span class="Delimiter">)</span>&<span class="Constant">0x7</span><span class="Delimiter">;</span> <span class="Comment">// middle 3 'reg opcode' bits</span> +<span id="L19" class="LineNr"> 19 </span> <span class="Normal">switch</span> <span class="Delimiter">(</span>subop<span class="Delimiter">)</span> <span class="Delimiter">{</span> +<span id="L20" class="LineNr"> 20 </span> <span class="Normal">case</span> <span class="Constant">0</span>: +<span id="L21" class="LineNr"> 21 </span> <span class="Conceal">¦</span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop add"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L22" class="LineNr"> 22 </span> <span class="Conceal">¦</span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>+<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L23" class="LineNr"> 23 </span> <span class="Conceal">¦</span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L24" class="LineNr"> 24 </span> <span class="Comment">// End Op 81 Subops</span> +<span id="L25" class="LineNr"> 25 </span> <span class="Normal">default</span>: +<span id="L26" class="LineNr"> 26 </span> <span class="Conceal">¦</span> cerr << <span class="Constant">"unrecognized sub-opcode after 81: "</span> << <a href='010core.cc.html#L220'>NUM</a><span class="Delimiter">(</span>subop<span class="Delimiter">)</span> << <span class="cSpecial">'\n'</span><span class="Delimiter">;</span> +<span id="L27" class="LineNr"> 27 </span> <span class="Conceal">¦</span> exit<span class="Delimiter">(</span><span class="Constant">1</span><span class="Delimiter">);</span> +<span id="L28" class="LineNr"> 28 </span> <span class="Delimiter">}</span> +<span id="L29" class="LineNr"> 29 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L30" class="LineNr"> 30 </span><span class="Delimiter">}</span> +<span id="L31" class="LineNr"> 31 </span> +<span id="L32" class="LineNr"> 32 </span><span class="Comment">//:</span> +<span id="L33" class="LineNr"> 33 </span> +<span id="L34" class="LineNr"> 34 </span><span class="Delimiter">:(scenario add_imm32_to_mem_at_r32)</span> +<span id="L35" class="LineNr"> 35 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L36" class="LineNr"> 36 </span><span class="Special">% Mem.at(0x60) = 1;</span> +<span id="L37" class="LineNr"> 37 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L38" class="LineNr"> 38 </span> <span class="Constant">81</span> <span class="PreProc">0</span><span class="Constant">3</span> 0a 0b 0c 0d <span class="Comment"># add 0x0d0c0b0a to *EBX (reg 3)</span> +<span id="L39" class="LineNr"> 39 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L40" class="LineNr"> 40 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L41" class="LineNr"> 41 </span><span class="traceContains">+run: subop add</span> +<span id="L42" class="LineNr"> 42 </span><span class="traceContains">+run: storing 0x0d0c0b0b</span> +<span id="L43" class="LineNr"> 43 </span> +<span id="L44" class="LineNr"> 44 </span><span class="SalientComment">//:: subtract</span> +<span id="L45" class="LineNr"> 45 </span> +<span id="L46" class="LineNr"> 46 </span><span class="Delimiter">:(scenario subtract_imm32_from_eax)</span> +<span id="L47" class="LineNr"> 47 </span><span class="Special">% Reg[EAX].i = 0x0d0c0baa;</span> +<span id="L48" class="LineNr"> 48 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L49" class="LineNr"> 49 </span> 2d 0a 0b 0c 0d <span class="Comment"># subtract 0x0d0c0b0a from EAX (reg 0)</span> +<span id="L50" class="LineNr"> 50 </span><span class="traceContains">+run: subtract <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a from <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a></span> +<span id="L51" class="LineNr"> 51 </span><span class="traceContains">+run: storing 0x000000a0</span> +<span id="L52" class="LineNr"> 52 </span> +<span id="L53" class="LineNr"> 53 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L54" class="LineNr"> 54 </span><span class="Normal">case</span> <span class="Constant">0x2d</span>: <span class="Delimiter">{</span> <span class="Comment">// subtract imm32 from EAX</span> +<span id="L55" class="LineNr"> 55 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> +<span id="L56" class="LineNr"> 56 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subtract <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" from <a href='010core.cc.html#L15'>reg</a> EAX"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L57" class="LineNr"> 57 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L58" class="LineNr"> 58 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L59" class="LineNr"> 59 </span><span class="Delimiter">}</span> +<span id="L60" class="LineNr"> 60 </span> +<span id="L61" class="LineNr"> 61 </span><span class="Comment">//:</span> +<span id="L62" class="LineNr"> 62 </span> +<span id="L63" class="LineNr"> 63 </span><span class="Delimiter">:(scenario subtract_imm32_from_mem_at_r32)</span> +<span id="L64" class="LineNr"> 64 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L65" class="LineNr"> 65 </span><span class="Special">% Mem.at(0x60) = 10;</span> +<span id="L66" class="LineNr"> 66 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L67" class="LineNr"> 67 </span> <span class="Constant">81</span> 2b <span class="PreProc">0</span><span class="Constant">1</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="Comment"># subtract 1 from *EBX (reg 3)</span> +<span id="L68" class="LineNr"> 68 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x00000001 with effective address</span> +<span id="L69" class="LineNr"> 69 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L70" class="LineNr"> 70 </span><span class="traceContains">+run: subop subtract</span> +<span id="L71" class="LineNr"> 71 </span><span class="traceContains">+run: storing 0x00000009</span> +<span id="L72" class="LineNr"> 72 </span> +<span id="L73" class="LineNr"> 73 </span><span class="Comment">//:</span> +<span id="L74" class="LineNr"> 74 </span> +<span id="L75" class="LineNr"> 75 </span><span class="Delimiter">:(scenario subtract_imm32_from_r32)</span> +<span id="L76" class="LineNr"> 76 </span><span class="Special">% Reg[3].i = 10;</span> +<span id="L77" class="LineNr"> 77 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L78" class="LineNr"> 78 </span> <span class="Constant">81</span> eb <span class="PreProc">0</span><span class="Constant">1</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="PreProc">0</span><span class="Constant">0</span> <span class="Comment"># subtract 1 from EBX (reg 3)</span> +<span id="L79" class="LineNr"> 79 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x00000001 with effective address</span> +<span id="L80" class="LineNr"> 80 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L81" class="LineNr"> 81 </span><span class="traceContains">+run: subop subtract</span> +<span id="L82" class="LineNr"> 82 </span><span class="traceContains">+run: storing 0x00000009</span> +<span id="L83" class="LineNr"> 83 </span> +<span id="L84" class="LineNr"> 84 </span><span class="Delimiter">:(before "End Op 81 Subops")</span> +<span id="L85" class="LineNr"> 85 </span><span class="Normal">case</span> <span class="Constant">5</span>: <span class="Delimiter">{</span> +<span id="L86" class="LineNr"> 86 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop subtract"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L87" class="LineNr"> 87 </span> <a href='010core.cc.html#L39'>BINARY_ARITHMETIC_OP</a><span class="Delimiter">(</span>-<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L88" class="LineNr"> 88 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L89" class="LineNr"> 89 </span><span class="Delimiter">}</span> +<span id="L90" class="LineNr"> 90 </span> +<span id="L91" class="LineNr"> 91 </span><span class="SalientComment">//:: and</span> +<span id="L92" class="LineNr"> 92 </span> +<span id="L93" class="LineNr"> 93 </span><span class="Delimiter">:(scenario and_imm32_with_eax)</span> +<span id="L94" class="LineNr"> 94 </span><span class="Special">% Reg[EAX].i = 0xff;</span> +<span id="L95" class="LineNr"> 95 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L96" class="LineNr"> 96 </span> <span class="Constant">25</span> 0a 0b 0c 0d <span class="Comment"># and 0x0d0c0b0a with EAX (reg 0)</span> +<span id="L97" class="LineNr"> 97 </span><span class="traceContains">+run: and <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a></span> +<span id="L98" class="LineNr"> 98 </span><span class="traceContains">+run: storing 0x0000000a</span> +<span id="L99" class="LineNr"> 99 </span> +<span id="L100" class="LineNr">100 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L101" class="LineNr">101 </span><span class="Normal">case</span> <span class="Constant">0x25</span>: <span class="Delimiter">{</span> <span class="Comment">// and imm32 with EAX</span> +<span id="L102" class="LineNr">102 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> +<span id="L103" class="LineNr">103 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"and <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" with <a href='010core.cc.html#L15'>reg</a> EAX"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L104" class="LineNr">104 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>&<span class="Delimiter">,</span> Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L105" class="LineNr">105 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L106" class="LineNr">106 </span><span class="Delimiter">}</span> +<span id="L107" class="LineNr">107 </span> +<span id="L108" class="LineNr">108 </span><span class="Comment">//:</span> +<span id="L109" class="LineNr">109 </span> +<span id="L110" class="LineNr">110 </span><span class="Delimiter">:(scenario and_imm32_with_mem_at_r32)</span> +<span id="L111" class="LineNr">111 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L112" class="LineNr">112 </span><span class="Special">% Mem.at(0x60) = 0xff;</span> +<span id="L113" class="LineNr">113 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L114" class="LineNr">114 </span> <span class="Constant">81</span> <span class="Constant">23</span> 0a 0b 0c 0d <span class="Comment"># and 0x0d0c0b0a with *EBX (reg 3)</span> +<span id="L115" class="LineNr">115 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L116" class="LineNr">116 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L117" class="LineNr">117 </span><span class="traceContains">+run: subop and</span> +<span id="L118" class="LineNr">118 </span><span class="traceContains">+run: storing 0x0000000a</span> +<span id="L119" class="LineNr">119 </span> +<span id="L120" class="LineNr">120 </span><span class="Comment">//:</span> +<span id="L121" class="LineNr">121 </span> +<span id="L122" class="LineNr">122 </span><span class="Delimiter">:(scenario and_imm32_with_r32)</span> +<span id="L123" class="LineNr">123 </span><span class="Special">% Reg[3].i = 0xff;</span> +<span id="L124" class="LineNr">124 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L125" class="LineNr">125 </span> <span class="Constant">81</span> e3 0a 0b 0c 0d <span class="Comment"># and 0x0d0c0b0a with EBX (reg 3)</span> +<span id="L126" class="LineNr">126 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L127" class="LineNr">127 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L128" class="LineNr">128 </span><span class="traceContains">+run: subop and</span> +<span id="L129" class="LineNr">129 </span><span class="traceContains">+run: storing 0x0000000a</span> +<span id="L130" class="LineNr">130 </span> +<span id="L131" class="LineNr">131 </span><span class="Delimiter">:(before "End Op 81 Subops")</span> +<span id="L132" class="LineNr">132 </span><span class="Normal">case</span> <span class="Constant">4</span>: <span class="Delimiter">{</span> +<span id="L133" class="LineNr">133 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop and"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L134" class="LineNr">134 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>&<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L135" class="LineNr">135 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L136" class="LineNr">136 </span><span class="Delimiter">}</span> +<span id="L137" class="LineNr">137 </span> +<span id="L138" class="LineNr">138 </span><span class="SalientComment">//:: or</span> +<span id="L139" class="LineNr">139 </span> +<span id="L140" class="LineNr">140 </span><span class="Delimiter">:(scenario or_imm32_with_eax)</span> +<span id="L141" class="LineNr">141 </span><span class="Special">% Reg[EAX].i = 0xd0c0b0a0;</span> +<span id="L142" class="LineNr">142 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L143" class="LineNr">143 </span> 0d 0a 0b 0c 0d <span class="Comment"># or 0x0d0c0b0a with EAX (reg 0)</span> +<span id="L144" class="LineNr">144 </span><span class="traceContains">+run: or <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a></span> +<span id="L145" class="LineNr">145 </span><span class="traceContains">+run: storing 0xddccbbaa</span> +<span id="L146" class="LineNr">146 </span> +<span id="L147" class="LineNr">147 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L148" class="LineNr">148 </span><span class="Normal">case</span> <span class="Constant">0x0d</span>: <span class="Delimiter">{</span> <span class="Comment">// or imm32 with EAX</span> +<span id="L149" class="LineNr">149 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> +<span id="L150" class="LineNr">150 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"or <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" with <a href='010core.cc.html#L15'>reg</a> EAX"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L151" class="LineNr">151 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>|<span class="Delimiter">,</span> Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L152" class="LineNr">152 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L153" class="LineNr">153 </span><span class="Delimiter">}</span> +<span id="L154" class="LineNr">154 </span> +<span id="L155" class="LineNr">155 </span><span class="Comment">//:</span> +<span id="L156" class="LineNr">156 </span> +<span id="L157" class="LineNr">157 </span><span class="Delimiter">:(scenario or_imm32_with_mem_at_r32)</span> +<span id="L158" class="LineNr">158 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L159" class="LineNr">159 </span><span class="Special">% Mem.at(0x60) = 0xa0;</span> +<span id="L160" class="LineNr">160 </span><span class="Special">% Mem.at(0x61) = 0xb0;</span> +<span id="L161" class="LineNr">161 </span><span class="Special">% Mem.at(0x62) = 0xc0;</span> +<span id="L162" class="LineNr">162 </span><span class="Special">% Mem.at(0x63) = 0xd0;</span> +<span id="L163" class="LineNr">163 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L164" class="LineNr">164 </span> <span class="Constant">81</span> 0b 0a 0b 0c 0d <span class="Comment"># or 0x0d0c0b0a with *EBX (reg 3)</span> +<span id="L165" class="LineNr">165 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L166" class="LineNr">166 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L167" class="LineNr">167 </span><span class="traceContains">+run: subop or</span> +<span id="L168" class="LineNr">168 </span><span class="traceContains">+run: storing 0xddccbbaa</span> +<span id="L169" class="LineNr">169 </span> +<span id="L170" class="LineNr">170 </span><span class="Comment">//:</span> +<span id="L171" class="LineNr">171 </span> +<span id="L172" class="LineNr">172 </span><span class="Delimiter">:(scenario or_imm32_with_r32)</span> +<span id="L173" class="LineNr">173 </span><span class="Special">% Reg[3].i = 0xd0c0b0a0;</span> +<span id="L174" class="LineNr">174 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L175" class="LineNr">175 </span> <span class="Constant">81</span> cb 0a 0b 0c 0d <span class="Comment"># or 0x0d0c0b0a with EBX (reg 3)</span> +<span id="L176" class="LineNr">176 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L177" class="LineNr">177 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L178" class="LineNr">178 </span><span class="traceContains">+run: subop or</span> +<span id="L179" class="LineNr">179 </span><span class="traceContains">+run: storing 0xddccbbaa</span> +<span id="L180" class="LineNr">180 </span> +<span id="L181" class="LineNr">181 </span><span class="Delimiter">:(before "End Op 81 Subops")</span> +<span id="L182" class="LineNr">182 </span><span class="Normal">case</span> <span class="Constant">1</span>: <span class="Delimiter">{</span> +<span id="L183" class="LineNr">183 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop or"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L184" class="LineNr">184 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>|<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L185" class="LineNr">185 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L186" class="LineNr">186 </span><span class="Delimiter">}</span> +<span id="L187" class="LineNr">187 </span> +<span id="L188" class="LineNr">188 </span><span class="SalientComment">//:: xor</span> +<span id="L189" class="LineNr">189 </span> +<span id="L190" class="LineNr">190 </span><span class="Delimiter">:(scenario xor_imm32_with_eax)</span> +<span id="L191" class="LineNr">191 </span><span class="Special">% Reg[EAX].i = 0xddccb0a0;</span> +<span id="L192" class="LineNr">192 </span><span class="Comment"># op ModR/M SIB displacement immediate</span> +<span id="L193" class="LineNr">193 </span> <span class="Constant">35</span> 0a 0b 0c 0d <span class="Comment"># xor 0x0d0c0b0a with EAX (reg 0)</span> +<span id="L194" class="LineNr">194 </span><span class="traceContains">+run: xor <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with <a href='010core.cc.html#L15'>reg</a> <a href='010core.cc.html#L5'>EAX</a></span> +<span id="L195" class="LineNr">195 </span><span class="traceContains">+run: storing 0xd0c0bbaa</span> +<span id="L196" class="LineNr">196 </span> +<span id="L197" class="LineNr">197 </span><span class="Delimiter">:(before "End Single-Byte Opcodes")</span> +<span id="L198" class="LineNr">198 </span><span class="Normal">case</span> <span class="Constant">0x35</span>: <span class="Delimiter">{</span> <span class="Comment">// xor imm32 with EAX</span> +<span id="L199" class="LineNr">199 </span> <span class="Normal">int32_t</span> arg2 = <a href='010core.cc.html#L207'>imm32</a><span class="Delimiter">();</span> +<span id="L200" class="LineNr">200 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"xor <a href='010core.cc.html#L207'>imm32</a> 0x"</span> << <a href='010core.cc.html#L218'>HEXWORD</a> << arg2 << <span class="Constant">" with <a href='010core.cc.html#L15'>reg</a> EAX"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L201" class="LineNr">201 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>^<span class="Delimiter">,</span> Reg[EAX]<span class="Delimiter">.</span><a href='010core.cc.html#L16'>i</a><span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L202" class="LineNr">202 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L203" class="LineNr">203 </span><span class="Delimiter">}</span> +<span id="L204" class="LineNr">204 </span> +<span id="L205" class="LineNr">205 </span><span class="Comment">//:</span> +<span id="L206" class="LineNr">206 </span> +<span id="L207" class="LineNr">207 </span><span class="Delimiter">:(scenario xor_imm32_with_mem_at_r32)</span> +<span id="L208" class="LineNr">208 </span><span class="Special">% Reg[3].i = 0x60;</span> +<span id="L209" class="LineNr">209 </span><span class="Special">% Mem.at(0x60) = 0xa0;</span> +<span id="L210" class="LineNr">210 </span><span class="Special">% Mem.at(0x61) = 0xb0;</span> +<span id="L211" class="LineNr">211 </span><span class="Special">% Mem.at(0x62) = 0xc0;</span> +<span id="L212" class="LineNr">212 </span><span class="Special">% Mem.at(0x63) = 0xd0;</span> +<span id="L213" class="LineNr">213 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L214" class="LineNr">214 </span> <span class="Constant">81</span> <span class="Constant">33</span> 0a 0b 0c 0d <span class="Comment"># xor 0x0d0c0b0a with *EBX (reg 3)</span> +<span id="L215" class="LineNr">215 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L216" class="LineNr">216 </span><span class="traceContains">+run: effective address is mem at address 0x60 (reg 3)</span> +<span id="L217" class="LineNr">217 </span><span class="traceContains">+run: subop xor</span> +<span id="L218" class="LineNr">218 </span><span class="traceContains">+run: storing 0xddccbbaa</span> +<span id="L219" class="LineNr">219 </span> +<span id="L220" class="LineNr">220 </span><span class="Comment">//:</span> +<span id="L221" class="LineNr">221 </span> +<span id="L222" class="LineNr">222 </span><span class="Delimiter">:(scenario xor_imm32_with_r32)</span> +<span id="L223" class="LineNr">223 </span><span class="Special">% Reg[3].i = 0xd0c0b0a0;</span> +<span id="L224" class="LineNr">224 </span><span class="Comment"># op ModRM SIB displacement immediate</span> +<span id="L225" class="LineNr">225 </span> <span class="Constant">81</span> f3 0a 0b 0c 0d <span class="Comment"># xor 0x0d0c0b0a with EBX (reg 3)</span> +<span id="L226" class="LineNr">226 </span><span class="traceContains">+run: combine <a href='010core.cc.html#L207'>imm32</a> 0x0d0c0b0a with effective address</span> +<span id="L227" class="LineNr">227 </span><span class="traceContains">+run: effective address is <a href='010core.cc.html#L15'>reg</a> 3</span> +<span id="L228" class="LineNr">228 </span><span class="traceContains">+run: subop xor</span> +<span id="L229" class="LineNr">229 </span><span class="traceContains">+run: storing 0xddccbbaa</span> +<span id="L230" class="LineNr">230 </span> +<span id="L231" class="LineNr">231 </span><span class="Delimiter">:(before "End Op 81 Subops")</span> +<span id="L232" class="LineNr">232 </span><span class="Normal">case</span> <span class="Constant">6</span>: <span class="Delimiter">{</span> +<span id="L233" class="LineNr">233 </span> <a href='003trace.cc.html#L160'>trace</a><span class="Delimiter">(</span><span class="Constant">2</span><span class="Delimiter">,</span> <span class="Constant">"run"</span><span class="Delimiter">)</span> << <span class="Constant">"subop xor"</span> << <a href='003trace.cc.html#L184'>end</a><span class="Delimiter">();</span> +<span id="L234" class="LineNr">234 </span> <a href='010core.cc.html#L49'>BINARY_BITWISE_OP</a><span class="Delimiter">(</span>^<span class="Delimiter">,</span> *arg1<span class="Delimiter">,</span> arg2<span class="Delimiter">);</span> +<span id="L235" class="LineNr">235 </span> <span class="Identifier">break</span><span class="Delimiter">;</span> +<span id="L236" class="LineNr">236 </span><span class="Delimiter">}</span> </pre> </body> </html> |