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| author | Kartik Agaram <vc@akkartik.com> | 2020-01-02 15:13:44 -0800 |
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| committer | Kartik Agaram <vc@akkartik.com> | 2020-01-02 15:13:44 -0800 |
| commit | 6f1581e77b8587da86a2fdaa461f83ab464447ce (patch) | |
| tree | 1d56c609c87e165c39b5cdce118b2a27bb7b4a97 | |
| parent | 300aa16720ddfa0b6e20aac020e42b701ffa6893 (diff) | |
| download | mu-6f1581e77b8587da86a2fdaa461f83ab464447ce.tar.gz | |
5874
| -rw-r--r-- | README.md | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/README.md b/README.md index 8fc74337..4686be6b 100644 --- a/README.md +++ b/README.md @@ -220,16 +220,10 @@ The registers instructions operate on are as follows: `6/esi` and `7/edi`. * Two additional 32-bit registers: `4/esp` and `5/ebp`. (I suggest you only use these to manage the call stack.) -* Four 1-bit _flag_ registers for conditional branching: - - zero/equal flag `ZF` - - sign flag `SF` - - overflow flag `OF` - - carry flag `CF` (SubX doesn't support floating-point registers yet. Intel processors support an 8-bit mode, 16-bit mode and 64-bit mode. SubX will never support them. -There are other flags. SubX will never support them. There are also _many_ -more instructions that SubX will never support.) +There are also _many_ more instructions that SubX will never support.) While SubX doesn't provide the usual mnemonics for opcodes, it _does_ provide error-checking. If you miss an argument or accidentally add an extra argument, |