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authorKartik Agaram <vc@akkartik.com>2020-09-27 21:12:48 -0700
committerKartik Agaram <vc@akkartik.com>2020-09-27 21:12:48 -0700
commit31e6ed17f84ff5b67803e534cde104b331dd495d (patch)
tree8ed6d9fe0eeea6d55489172c10d64909cddd7c05 /subx.md
parent7258083c6fe720b49c0a2b7e00af662dcb8a2d49 (diff)
downloadmu-31e6ed17f84ff5b67803e534cde104b331dd495d.tar.gz
6885 - starting on floating-point instructions
I spent some time deciding on the instructions. x87 is a stack ISA, so
not a good fit for the rest of SubX. So we use SSE instead. They operate
on 32-bit floats, which seems like a good fit.

SSE has a bunch of instructions for operating on up to 4 floats at once.
We'll ignore all that and just focus on so-called scalar instructions.
Diffstat (limited to 'subx.md')
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diff --git a/subx.md b/subx.md
index bd9f9d1f..a0004972 100644
--- a/subx.md
+++ b/subx.md
@@ -37,14 +37,17 @@ opcodes`.
 
 The registers instructions operate on are as follows:
 
-- Six general-purpose 32-bit registers: `0/eax`, `1/ebx`, `2/ecx`, `3/edx`,
-  `6/esi` and `7/edi`.
+- Six 32-bit integer registers: `0/eax`, `1/ebx`, `2/ecx`, `3/edx`, `6/esi`
+  and `7/edi`.
 - Two additional 32-bit registers: `4/esp` and `5/ebp`. (I suggest you only
   use these to manage the call stack.)
+- Eight 8-bit integer registers aliased with parts of the 32-bit registers:
+  `0/al`, `1/cl`, `2/dl`, `3/bl`, `4/ah`, `5/ch`, `6/dh` and `7/bh`.
+- Eight 32-bit floating-point registers: `xmm0` through `xmm7`.
 
-(SubX doesn't support floating-point registers yet. Intel processors support
-an 8-bit mode, 16-bit mode and 64-bit mode. SubX will never support them.
-There are also _many_ more instructions that SubX will never support.)
+(Intel processors support a 16-bit mode and 64-bit mode. SubX will never
+support them. There are also _many_ more instructions that SubX will never
+support.)
 
 While SubX doesn't provide the usual mnemonics for opcodes, it _does_ provide
 error-checking. If you miss an argument or accidentally add an extra argument,