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| author | Kartik K. Agaram <vc@akkartik.com> | 2017-10-18 01:42:51 -0700 |
|---|---|---|
| committer | Kartik K. Agaram <vc@akkartik.com> | 2017-10-18 01:44:52 -0700 |
| commit | f44c49c776b2199dd83b0de4e203a26bafa9c7ba (patch) | |
| tree | 1339971877f5f67ae96516be06e6f4c8244de801 /subx | |
| parent | 9e45873ff4a5af5fc2bb2fcab90accef171900f1 (diff) | |
| download | mu-f44c49c776b2199dd83b0de4e203a26bafa9c7ba.tar.gz | |
4080
subx: correct 'push' register. It gets its operand right from the opcode, not a new modrm byte. Have I misinterpreted any other instructions in this manner (`+rd` in the Intel manual)?
Diffstat (limited to 'subx')
| -rw-r--r-- | subx/011direct_addressing.cc | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/subx/011direct_addressing.cc b/subx/011direct_addressing.cc index 2defcfec..827ce41e 100644 --- a/subx/011direct_addressing.cc +++ b/subx/011direct_addressing.cc @@ -221,16 +221,22 @@ case 0x89: { // copy r32 to r/m32 % Reg[ESP].u = 0x64; % Reg[EBX].i = 10; # op ModRM SIB displacement immediate - 50 03 # push EBX (reg 3) to stack + 53 # push EBX (reg 3) to stack +run: push reg 3 +run: pushing value 0x0000000a +run: ESP is now 0x00000060 +run: contents at ESP: 0x0000000a :(before "End Single-Byte Opcodes") -case 0x50: { - uint8_t modrm = next(); - uint8_t reg = modrm & 0x7; +case 0x50: +case 0x51: +case 0x52: +case 0x53: +case 0x54: +case 0x55: +case 0x56: +case 0x57: { + uint8_t reg = op & 0x7; trace(2, "run") << "push reg " << NUM(reg) << end(); const int32_t val = Reg[reg].u; trace(2, "run") << "pushing value 0x" << HEXWORD << val << end(); |