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* 4078Kartik K. Agaram2017-10-171-1/+3
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* 4069Kartik K. Agaram2017-10-151-0/+2
| | | | subx: unconditional 'jump'
* 4068Kartik K. Agaram2017-10-151-3/+3
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* 4064Kartik K. Agaram2017-10-141-0/+4
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* 4062Kartik K. Agaram2017-10-131-0/+4
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* 4044Kartik K. Agaram2017-10-121-2/+1
| | | | subx: now starting on subtraction instructions.
* 4043Kartik K. Agaram2017-10-121-0/+1
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* 4040Kartik K. Agaram2017-10-121-2/+2
| | | | | | | subx: add immediate First example of a more complex opcode that needs to do its own decoding to decide what instruction to run.
* 4038Kartik K. Agaram2017-10-121-5/+7
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* 4037Kartik K. Agaram2017-10-121-1/+1
| | | | Fix non-standard switch statement.
* 4034Kartik K. Agaram2017-10-121-0/+2
| | | | Start implementing core x86 addressing mode decoding.
* 4032Kartik K. Agaram2017-10-121-13/+13
| | | | Consistent naming for the common terms 'register' and 'memory'.
* 4031Kartik K. Agaram2017-10-121-7/+7
| | | | | | No, go back to a vector for `Memory`. We need it to be contiguously laid out in memory so that we can write words all at once rather than a byte at a time.
* 4030Kartik K. Agaram2017-10-121-18/+53
| | | | Take control of hex byte parsing.
* 4029Kartik K. Agaram2017-10-121-25/+25
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* 4028Kartik K. Agaram2017-10-121-3/+3
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* 4026Kartik K. Agaram2017-10-121-29/+35
| | | | | | | | | | Make memory a sparse map rather than contiguous vector. In the process, a bugfix for `load_program`: support multiple lines of comments. Also save a local copy of the x86 cheatsheet I've been using: https://net.cs.uni-bonn.de/fileadmin/user_upload/plohmann/x86_opcode_structure_and_instruction_overview.pdf
* 4025Kartik K. Agaram2017-10-111-0/+1
| | | | Fix CI.
* 4023Kartik K. Agaram2017-10-111-4/+4
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* 4022Kartik K. Agaram2017-10-111-2/+4
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* 4021Kartik K. Agaram2017-10-111-2/+2
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* 4019Kartik K. Agaram2017-10-111-4/+4
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* 4018Kartik K. Agaram2017-10-111-3/+3
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* 4017Kartik K. Agaram2017-10-111-6/+6
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* 4014 - core skeleton for x86 interpreterKartik K. Agaram2017-10-111-0/+173