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* 4168Kartik K. Agaram2017-12-301-52/+52
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* 4162Kartik K. Agaram2017-12-221-25/+0
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* 4085 - done with first cut of the SubX VMKartik K. Agaram2017-10-182-3/+80
| | | | subx: 'call' and 'return' instructions
* 4084Kartik K. Agaram2017-10-182-25/+24
| | | | | subx: extract helpers for 'push' and 'pop'. We will be using them in 'call' and 'ret' as well.
* 4083Kartik K. Agaram2017-10-182-1/+60
| | | | subx: 'pop'
* 4082Kartik K. Agaram2017-10-182-5/+11
| | | | | subx: correct a 'copy' ('mov') instruction as well to get its operand right from the opcode.
* 4081Kartik K. Agaram2017-10-181-16/+12
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* 4080Kartik K. Agaram2017-10-181-4/+10
| | | | | | | | subx: correct 'push' register. It gets its operand right from the opcode, not a new modrm byte. Have I misinterpreted any other instructions in this manner (`+rd` in the Intel manual)?
* 4079Kartik K. Agaram2017-10-183-7/+82
| | | | subx: 'pop'
* 4078Kartik K. Agaram2017-10-171-1/+3
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* 4076Kartik K. Agaram2017-10-161-1/+1
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* 4075Kartik K. Agaram2017-10-161-3/+4
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* 4074Kartik K. Agaram2017-10-161-6/+10
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* 4073Kartik K. Agaram2017-10-161-4/+7
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* 4071Kartik K. Agaram2017-10-163-46/+510
| | | | | | | | | subx: conditional jump instructions Lots of boilerplate here. This commit really strains my 'copyista' ethic. But I think it's still clearer to see each instruction implemented independently than to try to create a macro or something like that.
* 4070Kartik K. Agaram2017-10-151-0/+11
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* 4069Kartik K. Agaram2017-10-153-0/+80
| | | | subx: unconditional 'jump'
* 4068Kartik K. Agaram2017-10-151-3/+3
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* 4067Kartik K. Agaram2017-10-153-3/+92
| | | | subx: 'mov'
* 4066Kartik K. Agaram2017-10-142-2/+2
| | | | | | I spent a while spelunking into the code generated by C compilers before realizing that ignoring the order of arguments for 'cmp' instructions clarifies everything.
* 4065Kartik K. Agaram2017-10-143-0/+228
| | | | | | subx: 'compare' Hopefully I've implemented the 'sense' of comparisons right..
* 4064Kartik K. Agaram2017-10-143-41/+20
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* 4063Kartik K. Agaram2017-10-141-2/+2
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* 4062Kartik K. Agaram2017-10-131-0/+4
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* 4061Kartik K. Agaram2017-10-131-5/+5
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* 4060 - subx: correct stale ReadmeKartik K. Agaram2017-10-131-7/+1
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* 4058Kartik K. Agaram2017-10-132-0/+38
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* 4057Kartik K. Agaram2017-10-133-0/+111
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* 4056Kartik K. Agaram2017-10-133-0/+111
| | | | subx: 'or'
* 4055Kartik K. Agaram2017-10-133-0/+105
| | | | subx: Implement 'and' for the addressing modes we've built so far.
* 4053Kartik K. Agaram2017-10-122-5/+5
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* 4051Kartik K. Agaram2017-10-123-74/+74
| | | | subx: Move register direct mode before indirect in the exposition.
* 4050Kartik K. Agaram2017-10-121-0/+18
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* 4049Kartik K. Agaram2017-10-123-99/+101
| | | | Instead of organizing layers by instruction, do so by addressing mode.
* 4048Kartik K. Agaram2017-10-121-0/+22
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* 4047Kartik K. Agaram2017-10-121-0/+22
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* 4046Kartik K. Agaram2017-10-121-0/+12
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* 4045Kartik K. Agaram2017-10-121-3/+24
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* 4044Kartik K. Agaram2017-10-122-2/+18
| | | | subx: now starting on subtraction instructions.
* 4043Kartik K. Agaram2017-10-122-2/+25
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* 4042Kartik K. Agaram2017-10-121-4/+15
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* 4041Kartik K. Agaram2017-10-121-0/+4
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* 4040Kartik K. Agaram2017-10-122-3/+37
| | | | | | | subx: add immediate First example of a more complex opcode that needs to do its own decoding to decide what instruction to run.
* 4039Kartik K. Agaram2017-10-121-3/+3
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* 4038Kartik K. Agaram2017-10-122-8/+10
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* 4037Kartik K. Agaram2017-10-122-12/+15
| | | | Fix non-standard switch statement.
* 4036Kartik K. Agaram2017-10-121-6/+6
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* 4035Kartik K. Agaram2017-10-121-0/+3
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* 4034Kartik K. Agaram2017-10-123-0/+58
| | | | Start implementing core x86 addressing mode decoding.
* 4033Kartik K. Agaram2017-10-121-1/+0
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