Add stuff

author: Crystal <crystal@wizard.tower> 2024-02-24 18:23:19 +0100
committer: Crystal <crystal@wizard.tower> 2024-02-24 18:23:19 +0100
commit: 059c5ab9a67e2ddf45fffc792bcc53b177c87dfe (patch)
tree: e0e0606d10ec87a0c87691f36f485e1247ea3d61
parent: b56073daf271031c8e8a2b0d84df81383eea7eca (diff)
download: www-059c5ab9a67e2ddf45fffc792bcc53b177c87dfe.tar.gz
2 files changed, 168 insertions, 16 deletions
diff --git a/blog/asm/1.html b/blog/asm/1.html
index e9efd34..f283a63 100644
--- a/blog/asm/1.html
+++ b/blog/asm/1.html
@@ -3,7 +3,7 @@
 "http://www.w3.org/TR/xhtml1/DTD/xhtml1-strict.dtd">
 <html xmlns="http://www.w3.org/1999/xhtml" lang="en" xml:lang="en">
 <head>
-<!-- 2024-02-24 Sat 17:36 -->
+<!-- 2024-02-24 Sat 18:22 -->
 <meta http-equiv="Content-Type" content="text/html;charset=utf-8" />
 <meta name="viewport" content="width=device-width, initial-scale=1" />
 <title>x86 Assembly from my understanding</title>
@@ -23,9 +23,9 @@
 <p>
 Soooo this article (or maybe even a series of articles, who knows ?) will be about x86 assembly, or rather, what I understood from it and my road from the bottom-up hopefully reaching a good level of understanding
 </p>
-<div id="outline-container-org8392211" class="outline-2">
-<h2 id="org8392211">Memory :</h2>
-<div class="outline-text-2" id="text-org8392211">
+<div id="outline-container-org0804bec" class="outline-2">
+<h2 id="org0804bec">Memory :</h2>
+<div class="outline-text-2" id="text-org0804bec">
 <p>
 Memory is a sequence of octets (Aka 8bits) that each have a unique integer assigned to them called <b>The Effective Address (EA)</b>, in this particular CPU Architecture (the i8086), the octet is designated by a couple (A segment number, and the offset in the segment)
 </p>
@@ -40,9 +40,9 @@ Memory is a sequence of octets (Aka 8bits) that each have a unique integer assig
 The offset and segment are encoded in 16bits, so they take a value between 0 and 65535
 </p>
 </div>
-<div id="outline-container-orgb021039" class="outline-4">
-<h4 id="orgb021039">Important :</h4>
-<div class="outline-text-4" id="text-orgb021039">
+<div id="outline-container-org91745ea" class="outline-4">
+<h4 id="org91745ea">Important :</h4>
+<div class="outline-text-4" id="text-org91745ea">
 <p>
 The relation between the Effective Address and the Segment &amp; Offset is as follow :
 </p>
@@ -52,8 +52,8 @@ The relation between the Effective Address and the Segment &amp; Offset is as fo
 </p>
 </div>
 <ul class="org-ul">
-<li><a id="orgda02cd3"></a>Example :<br />
-<div class="outline-text-5" id="text-orgda02cd3">
+<li><a id="orge330b02"></a>Example :<br />
+<div class="outline-text-5" id="text-orge330b02">
 <p>
 Let the Physical address (Or Effective Address, these two terms are enterchangeable) <b>12345h</b> (the h refers to Hexadecimal, which can also be written like this <b>0x12345</b>), the register <b>DS = 1230h</b> and the register <b>SI = 0045h</b>, the CPU calculates the physical address by multiplying the content of the segment register <b>DS</b> by 10h (or 16) and adding the content of the register <b>SI</b>. so we get : <b>1230h x 10h + 45h = 12345h</b>
 </p>
@@ -66,16 +66,16 @@ Now if you are a clever one ( I know you are, since you are reading this &lt;3 )
 </li>
 </ul>
 </div>
-<div id="outline-container-orgd56c9fa" class="outline-3">
-<h3 id="orgd56c9fa">Registers</h3>
-<div class="outline-text-3" id="text-orgd56c9fa">
+<div id="outline-container-org90039d0" class="outline-3">
+<h3 id="org90039d0">Registers</h3>
+<div class="outline-text-3" id="text-org90039d0">
 <p>
 The 8086 CPU has 14 registers of 16bits of size. From the POV of the user, the 8086 has 3 groups of 4 registers of 16bits. One state register of 9bits and a counting program of 16bits inaccessible to the user (whatever this means).
 </p>
 </div>
-<div id="outline-container-orgd10cc4b" class="outline-4">
-<h4 id="orgd10cc4b">General Registers</h4>
-<div class="outline-text-4" id="text-orgd10cc4b">
+<div id="outline-container-org758d630" class="outline-4">
+<h4 id="org758d630">General Registers</h4>
+<div class="outline-text-4" id="text-org758d630">
 <p>
 General registers contribute to arithmetic&rsquo;s and logic and addressing too.
 </p>
@@ -106,6 +106,108 @@ Now here are the Registers we can find in this section:
 <pre class="src src-asm"><span style="color: #89b4fa;">MOV</span> <span style="color: #cba6f7;">BL</span>, [<span style="color: #fab387;">500</span>] <span style="color: #6c7086;">;</span><span style="color: #6c7086;">(BL = 500H)</span>
 </pre>
 </div>
+
+<p>
+<b>CX</b>: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL to also perform 8-bit instructions. It is used in looping and rotation. Example:
+</p>
+<div class="org-src-container">
+<pre class="src src-asm"><span style="color: #89b4fa;">MOV</span> <span style="color: #cba6f7;">CX</span>, <span style="color: #fab387;">0005</span>
+<span style="color: #89b4fa;">LOOP</span>
+</pre>
+</div>
+
+<p>
+<b>DX</b>: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to also perform 8-bit instructions. It is used in the multiplication and input/output port addressing. Example:
+</p>
+<div class="org-src-container">
+<pre class="src src-asm"><span style="color: #89b4fa;">MUL</span> <span style="color: #cba6f7;">BX</span> (DX, AX = AX * BX)
+</pre>
+</div>
+</div>
+</div>
+<div id="outline-container-org810d22b" class="outline-4">
+<h4 id="org810d22b">Offset/Address Registers</h4>
+<div class="outline-text-4" id="text-org810d22b">
+<p>
+<b>SP</b>: This is the stack pointer. It is of 16 bits. It points to the topmost item of the stack. If the stack is empty the stack pointer will be (FFFE)H (or 65534 in decimal). Its offset address is relative to the stack segment(SS).
+</p>
+
+<p>
+<b>BP</b>: This is the base pointer. It is of 16 bits. It is primarily used in accessing parameters passed by the stack. Its offset address is relative to the stack segment(SS).
+</p>
+
+<p>
+<b>SI</b>: This is the source index register. It is of 16 bits. It is used in the pointer addressing of data and as a source in some string-related operations. Its offset is relative to the data segment(DS).
+</p>
+
+<p>
+<b>DI</b>: This is the destination index register. It is of 16 bits. It is used in the pointer addressing of data and as a destination in some string-related operations. Its offset is relative to the extra segment(ES).
+</p>
+</div>
+</div>
+<div id="outline-container-orgfd6556c" class="outline-4">
+<h4 id="orgfd6556c">Segment Registers</h4>
+<div class="outline-text-4" id="text-orgfd6556c">
+<p>
+<b>CS</b>: Code Segment, it defines the start of the program memory, and the different addresses of the different instructions relative to CS.
+</p>
+
+<p>
+<b>DS</b>: Data Segment, defines the start of the data memory where we store all data processed by the program.
+</p>
+
+<p>
+<b>SS</b>: Stack Segment, or the start of the pile. The pile is a memory zone that is managed in a particular way, it&rsquo;s like a pile of plates, where we can only remove and add plates on top of the pile. Only one address register is enough to manage it, its the stack pointer SP. We say that this pile is a LIFO pile (Last IN, First OUT)
+</p>
+
+<p>
+<b>EX</b>: The start of an auxiliary segment for data
+</p>
+</div>
+</div>
+</div>
+<div id="outline-container-orgb663ae9" class="outline-3">
+<h3 id="orgb663ae9">The format of an address:</h3>
+<div class="outline-text-3" id="text-orgb663ae9">
+<p>
+An Address must have this fellowing form [RS : RO] with the following possibilities:
+</p>
+
+<ul class="org-ul">
+<li>A value : Nothing</li>
+<li>ES : DI</li>
+<li>CS : SI</li>
+<li>ES : BP</li>
+<li>DS : BX</li>
+</ul>
+</div>
+<div id="outline-container-orgc26de48" class="outline-4">
+<h4 id="orgc26de48">Note 1 :</h4>
+<div class="outline-text-4" id="text-orgc26de48">
+<p>
+When the register isn&rsquo;t specified. the CPU adds it depending on the offset used :
+</p>
+
+<ul class="org-ul">
+<li>If the offset is : DI SI or BX, the Segment used is DS.</li>
+<li>If its BP, then the segment is SS.</li>
+</ul>
+</div>
+</div>
+<div id="outline-container-orgc918fef" class="outline-4">
+<h4 id="orgc918fef">Note 2 :</h4>
+<div class="outline-text-4" id="text-orgc918fef">
+<p>
+Apparently we will assume that we are in the DS segment and only access to memory using the offset.
+</p>
+</div>
+</div>
+<div id="outline-container-org4affc44" class="outline-4">
+<h4 id="org4affc44">Note 3 :</h4>
+<div class="outline-text-4" id="text-org4affc44">
+<p>
+The values of the registers CS DS and SS are automatically initialized by the OS when launching the program. So these segments are implicit. AKA : If we want to access a specific data in memory, we just need to specify its offset.
+</p>
 </div>
 </div>
 </div>
@@ -113,7 +215,7 @@ Now here are the Registers we can find in this section:
 </div>
 <div id="postamble" class="status">
 <p class="author">Author: Crystal</p>
-<p class="date">Created: 2024-02-24 Sat 17:36</p>
+<p class="date">Created: 2024-02-24 Sat 18:22</p>
 </div>
 </body>
 </html>
diff --git a/src/org/blog/assembly/1.org b/src/org/blog/assembly/1.org
index f5a1a59..daa4976 100644
--- a/src/org/blog/assembly/1.org
+++ b/src/org/blog/assembly/1.org
@@ -57,3 +57,53 @@ ADD AX, AX ;(AX = AX + AX)
 #+BEGIN_SRC asm
 MOV BL, [500] ;(BL = 500H)
 #+END_SRC
+
+*CX*: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL to also perform 8-bit instructions. It is used in looping and rotation. Example:
+#+BEGIN_SRC asm
+MOV CX, 0005
+LOOP
+#+END_SRC
+
+*DX*: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to also perform 8-bit instructions. It is used in the multiplication and input/output port addressing. Example:
+#+BEGIN_SRC asm
+MUL BX (DX, AX = AX * BX)
+#+END_SRC
+
+*** Offset/Address Registers
+*SP*: This is the stack pointer. It is of 16 bits. It points to the topmost item of the stack. If the stack is empty the stack pointer will be (FFFE)H (or 65534 in decimal). Its offset address is relative to the stack segment(SS).
+
+*BP*: This is the base pointer. It is of 16 bits. It is primarily used in accessing parameters passed by the stack. Its offset address is relative to the stack segment(SS).
+
+*SI*: This is the source index register. It is of 16 bits. It is used in the pointer addressing of data and as a source in some string-related operations. Its offset is relative to the data segment(DS).
+
+*DI*: This is the destination index register. It is of 16 bits. It is used in the pointer addressing of data and as a destination in some string-related operations. Its offset is relative to the extra segment(ES).
+
+*** Segment Registers
+*CS*: Code Segment, it defines the start of the program memory, and the different addresses of the different instructions relative to CS.
+
+*DS*: Data Segment, defines the start of the data memory where we store all data processed by the program.
+
+*SS*: Stack Segment, or the start of the pile. The pile is a memory zone that is managed in a particular way, it's like a pile of plates, where we can only remove and add plates on top of the pile. Only one address register is enough to manage it, its the stack pointer SP. We say that this pile is a LIFO pile (Last IN, First OUT)
+
+*EX*: The start of an auxiliary segment for data
+
+** The format of an address:
+An Address must have this fellowing form [RS : RO] with the following possibilities:
+
+- A value : Nothing
+- ES : DI
+- CS : SI
+- ES : BP
+- DS : BX
+
+*** Note 1 :
+When the register isn't specified. the CPU adds it depending on the offset used :
+
+- If the offset is : DI SI or BX, the Segment used is DS.
+- If its BP, then the segment is SS.
+
+*** Note 2 :
+Apparently we will assume that we are in the DS segment and only access to memory using the offset.
+
+*** Note 3 :
+The values of the registers CS DS and SS are automatically initialized by the OS when launching the program. So these segments are implicit. AKA : If we want to access a specific data in memory, we just need to specify its offset.
author	Crystal <crystal@wizard.tower>	2024-02-24 18:23:19 +0100
committer	Crystal <crystal@wizard.tower>	2024-02-24 18:23:19 +0100
commit	059c5ab9a67e2ddf45fffc792bcc53b177c87dfe (patch)
tree	e0e0606d10ec87a0c87691f36f485e1247ea3d61
parent	b56073daf271031c8e8a2b0d84df81383eea7eca (diff)
download	www-059c5ab9a67e2ddf45fffc792bcc53b177c87dfe.tar.gz